From bbb06d9ec69c88de2a198e130dfb90d7151cf68d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Mon, 6 Nov 2023 19:57:02 +0100 Subject: [PATCH] Add Ssdtso extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Ssdtso extension adds a DTSO bit to the {m,s,h}envcfg registers to enable TSO. Since Spike is sequentially consistent it always operates TSO-compatible. Therefore, all we have to do is make Spike aware of the extension (reading and writing the {m,s,h}envcfg register already exists and we don't use the bit inside of Spike anywhere). For completeness, this patch also defines the {M,S,H}ENVCFG_DTSO mask macros, even if they are not used anywhere. Signed-off-by: Christoph Müllner --- README.md | 1 + disasm/isa_parser.cc | 2 ++ riscv/encoding.h | 3 +++ riscv/isa_parser.h | 1 + 4 files changed, 7 insertions(+) diff --git a/README.md b/README.md index 2c5bba9145..6d898d9546 100644 --- a/README.md +++ b/README.md @@ -43,6 +43,7 @@ Spike supports the following RISC-V ISA features: - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 + - Ssdtso v1.0 - Zca extension, v1.0 - Zcb extension, v1.0 - Zcf extension, v1.0 diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index ef513108d1..2760b35019 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -292,6 +292,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_SMCSRIND] = true; } else if (ext_str == "sscsrind") { extension_table[EXT_SSCSRIND] = true; + } else if (ext_str == "ssdtso") { + extension_table[EXT_SSDTSO] = true; } else if (ext_str == "smcntrpmf") { extension_table[EXT_SMCNTRPMF] = true; } else if (ext_str == "zcmop") { diff --git a/riscv/encoding.h b/riscv/encoding.h index 81d829cf15..2bf43c15db 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -160,6 +160,7 @@ #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 +#define MENVCFG_DTSO 0x00000100 #define MENVCFG_ADUE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 #define MENVCFG_STCE 0x8000000000000000 @@ -198,6 +199,7 @@ #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 #define HENVCFG_CBZE 0x00000080 +#define HENVCFG_DTSO 0x00000100 #define HENVCFG_ADUE 0x2000000000000000 #define HENVCFG_PBMTE 0x4000000000000000 #define HENVCFG_STCE 0x8000000000000000 @@ -233,6 +235,7 @@ #define SENVCFG_CBIE 0x00000030 #define SENVCFG_CBCFE 0x00000040 #define SENVCFG_CBZE 0x00000080 +#define SENVCFG_DTSO 0x00000100 #define SSTATEEN0_CS 0x00000001 #define SSTATEEN0_FCSR 0x00000002 diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index a84b6fe8d7..f91cf67f78 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -80,6 +80,7 @@ typedef enum { EXT_INTERNAL_ZFH_MOVE, EXT_SMCSRIND, EXT_SSCSRIND, + EXT_SSDTSO, EXT_SMCNTRPMF, EXT_ZCMOP, EXT_ZALASR,