Merge pull request #1860 from XYenChi/master

aswaterman · web-flow · commit eb0a3e2b0a7c · 2024-11-20T09:27:19.000-08:00
Fix formatting of assembly code within comments
diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h
@@ -1,4 +1,4 @@
-// vmulhu vd ,vs2, vs1
+// vmulhu vd, vs2, vs1
 VI_VV_ULOOP
 ({
   vd = ((uint128_t)vs2 * vs1) >> sew;
diff --git a/riscv/insns/vredand_vs.h b/riscv/insns/vredand_vs.h
@@ -1,4 +1,4 @@
-// vredand.vs vd, vs2 ,vs1
+// vredand.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res &= vs2;
diff --git a/riscv/insns/vredmaxu_vs.h b/riscv/insns/vredmaxu_vs.h
@@ -1,4 +1,4 @@
-// vredmaxu.vs vd, vs2 ,vs1
+// vredmaxu.vs vd, vs2, vs1
 VI_VV_ULOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2;
diff --git a/riscv/insns/vredmin_vs.h b/riscv/insns/vredmin_vs.h
@@ -1,4 +1,4 @@
-// vredmin.vs vd, vs2 ,vs1
+// vredmin.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;
diff --git a/riscv/insns/vredminu_vs.h b/riscv/insns/vredminu_vs.h
@@ -1,4 +1,4 @@
-// vredminu.vs vd, vs2 ,vs1
+// vredminu.vs vd, vs2, vs1
 VI_VV_ULOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;
diff --git a/riscv/insns/vredor_vs.h b/riscv/insns/vredor_vs.h
@@ -1,4 +1,4 @@
-// vredor.vs vd, vs2 ,vs1
+// vredor.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res |= vs2;
diff --git a/riscv/insns/vredsum_vs.h b/riscv/insns/vredsum_vs.h
@@ -1,4 +1,4 @@
-// vredsum.vs vd, vs2 ,vs1
+// vredsum.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res += vs2;
diff --git a/riscv/insns/vredxor_vs.h b/riscv/insns/vredxor_vs.h
@@ -1,4 +1,4 @@
-// vredxor.vs vd, vs2 ,vs1
+// vredxor.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res ^= vs2;

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vmulhu vd ,vs2, vs1`
	`1`	`+// vmulhu vd, vs2, vs1`
`2`	`2`	`VI_VV_ULOOP`
`3`	`3`	`({`
`4`	`4`	`vd = ((uint128_t)vs2 * vs1) >> sew;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredand.vs vd, vs2 ,vs1`
	`1`	`+// vredand.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_LOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res &= vs2;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredmaxu.vs vd, vs2 ,vs1`
	`1`	`+// vredmaxu.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_ULOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredmin.vs vd, vs2 ,vs1`
	`1`	`+// vredmin.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_LOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredminu.vs vd, vs2 ,vs1`
	`1`	`+// vredminu.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_ULOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredor.vs vd, vs2 ,vs1`
	`1`	`+// vredor.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_LOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res \|= vs2;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredsum.vs vd, vs2 ,vs1`
	`1`	`+// vredsum.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_LOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res += vs2;`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// vredxor.vs vd, vs2 ,vs1`
	`1`	`+// vredxor.vs vd, vs2, vs1`
`2`	`2`	`VI_VV_LOOP_REDUCTION`
`3`	`3`	`({`
`4`	`4`	`vd_0_res ^= vs2;`