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Merge pull request #1997 from riscv-software-src/fix-1996
Partially revert #1987 to fix regrssion in vsra.vi and vssra.vi
2 parents a07c190 + 37db712 commit a3dbcba

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3 files changed

+6
-6
lines changed

3 files changed

+6
-6
lines changed

riscv/insns/vsra_vi.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// vsra.vi vd, vs2, zimm5
2-
VI_VI_ULOOP
2+
VI_VI_LOOP
33
({
4-
vd = vs2 >> (zimm5 & (sew - 1));
4+
vd = vs2 >> (insn.v_zimm5() & (sew - 1));
55
})

riscv/insns/vssra_vi.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// vssra.vi vd, vs2, zimm5
2-
VI_VI_ULOOP
2+
VI_VI_LOOP
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({
44
VRM xrm = P.VU.get_vround_mode();
5-
int sh = zimm5 & (sew - 1);
5+
int sh = insn.v_zimm5() & (sew - 1);
66
int128_t val = vs2;
77

88
INT_ROUNDING(val, xrm, sh);

riscv/v_ext_macros.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
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require_vector(true); \
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reg_t vl = P.VU.vl->read(); \
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reg_t UNUSED sew = P.VU.vsew; \
203-
reg_t rd_num = insn.rd(); \
203+
reg_t UNUSED rd_num = insn.rd(); \
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reg_t UNUSED rs1_num = insn.rs1(); \
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reg_t rs2_num = insn.rs2(); \
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for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
@@ -336,7 +336,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
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#define VI_PARAMS(x) \
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type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \
339-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5(); \
339+
type_sew_t<x>::type UNUSED simm5 = (type_sew_t<x>::type)insn.v_simm5(); \
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type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i);
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#define XV_PARAMS(x) \

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