[vector-crypto] Fixing Zvkb/Zvbb distinction

nibrunie · nibrunieAtSi5 · commit 9cddf2076b5c · 2024-07-22T13:00:54.000-07:00
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc
@@ -257,6 +257,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZVFBFMIN] = true;
     } else if (ext_str == "zvfbfwma") {
       extension_table[EXT_ZVFBFWMA] = true;
+    } else if (ext_str == "zvkb") {
+      extension_table[EXT_ZVKB] = true;
     } else if (ext_str == "zvkg") {
       extension_table[EXT_ZVKG] = true;
     } else if (ext_str == "zvkn") {
diff --git a/riscv/insns/vandn_vv.h b/riscv/insns/vandn_vv.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 VI_VV_LOOP
 ({
diff --git a/riscv/insns/vandn_vx.h b/riscv/insns/vandn_vx.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 VI_VX_LOOP
 ({
diff --git a/riscv/insns/vbrev8_v.h b/riscv/insns/vbrev8_v.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 VI_V_ULOOP
 ({
diff --git a/riscv/insns/vrev8_v.h b/riscv/insns/vrev8_v.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 VI_V_ULOOP
 ({
diff --git a/riscv/insns/vrol_vv.h b/riscv/insns/vrol_vv.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 // 'mask' selects the low log2(vsew) bits of the shift amount,
 // to limit the maximum shift to "vsew - 1" bits.
diff --git a/riscv/insns/vrol_vx.h b/riscv/insns/vrol_vx.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 // 'mask' selects the low log2(vsew) bits of the shift amount,
 // to limit the maximum shift to "vsew - 1" bits.
diff --git a/riscv/insns/vror_vi.h b/riscv/insns/vror_vi.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 // 'mask' selects the low log2(vsew) bits of the shift amount,
 // to limit the maximum shift to "vsew - 1" bits.
diff --git a/riscv/insns/vror_vv.h b/riscv/insns/vror_vv.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 // 'mask' selects the low log2(vsew) bits of the shift amount,
 // to limit the maximum shift to "vsew - 1" bits.
diff --git a/riscv/insns/vror_vx.h b/riscv/insns/vror_vx.h
@@ -2,7 +2,7 @@
 
 #include "zvk_ext_macros.h"
 
-require_zvbb;
+require_zvkb;
 
 // 'mask' selects the low log2(vsew) bits of the shift amount,
 // to limit the maximum shift to "vsew - 1" bits.
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h
@@ -59,6 +59,7 @@ typedef enum {
   EXT_ZVBC,
   EXT_ZVFBFMIN,
   EXT_ZVFBFWMA,
+  EXT_ZVKB,
   EXT_ZVKG,
   EXT_ZVKNED,
   EXT_ZVKNHA,
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
@@ -1005,20 +1005,23 @@ riscv_insn_ext_zalasr = \
 	sw_rl \
 	sd_rl \
 
-riscv_insn_ext_zvbb = \
+riscv_insn_ext_zvkb = \
 	vandn_vv \
 	vandn_vx \
 	vbrev8_v \
-	vbrev_v \
-	vclz_v \
-	vcpop_v \
-	vctz_v \
 	vrev8_v \
 	vrol_vv \
 	vrol_vx \
 	vror_vi \
 	vror_vv \
 	vror_vx \
+
+riscv_insn_ext_zvbb = \
+    $(riscv_insn_ext_zvkb) \
+	vbrev_v \
+	vclz_v \
+	vcpop_v \
+	vctz_v \
 	vwsll_vi \
 	vwsll_vv \
 	vwsll_vx \
diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h
@@ -13,7 +13,7 @@
 // Predicate Macros
 //
 
-// Ensures that the ZVBB extension (vector crypto bitmanip) is present,
+// Ensures that the ZVBB extension (vector basic bitmanip) is present,
 // and the vector unit is enabled and in a valid state.
 #define require_zvbb \
   do { \
@@ -29,6 +29,14 @@
     require_extension(EXT_ZVBC); \
   } while (0)
 
+// Ensures that the ZVKB extension (vector crypto bitmanip) is present,
+// and the vector unit is enabled and in a valid state.
+#define require_zvkb \
+  do { \
+    require_vector(true); \
+    require_extension(EXT_ZVKB); \
+  } while (0)
+
 // Ensures that the ZVKG extension (vector Galois Field Multiplication)
 // is present, and the vector unit is enabled and in a valid state.
 #define require_zvkg \
