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pointer masking: Let cache-block management instructions take into account pointer masking
1 parent 42776e6 commit 91173cb

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+7
-4
lines changed

1 file changed

+7
-4
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riscv/mmu.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -232,16 +232,19 @@ class mmu_t
232232
}
233233

234234
void clean_inval(reg_t addr, bool clean, bool inval) {
235-
auto base = addr & ~(blocksz - 1);
235+
auto access_info = generate_access_info(addr, LOAD, {});
236+
reg_t transformed_addr = access_info.transformed_vaddr;
237+
238+
auto base = transformed_addr & ~(blocksz - 1);
236239
for (size_t offset = 0; offset < blocksz; offset += 1)
237-
check_triggers(triggers::OPERATION_STORE, base + offset, false, addr, std::nullopt);
240+
check_triggers(triggers::OPERATION_STORE, base + offset, false, transformed_addr, std::nullopt);
238241
convert_load_traps_to_store_traps({
239-
const reg_t paddr = translate(generate_access_info(addr, LOAD, {}), 1);
242+
const reg_t paddr = translate(generate_access_info(transformed_addr, LOAD, {}), 1);
240243
if (sim->reservable(paddr)) {
241244
if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
242245
tracer.clean_invalidate(paddr, blocksz, clean, inval);
243246
} else {
244-
throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0);
247+
throw trap_store_access_fault((proc) ? proc->state.v : false, transformed_addr, 0, 0);
245248
}
246249
})
247250
}

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