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Merge pull request #1740 from YenHaoChen/pr-fcvtmod_w_d
fcvtmod.w.d: Not update fflags if no exception flag, e.g., exp == frac == 0
2 parents 7dce838 + e86e653 commit 64bc0c1

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2 files changed

+7
-6
lines changed

2 files changed

+7
-6
lines changed

riscv/decode_macros.h

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -211,10 +211,12 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
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} \
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} while (0);
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214-
#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
215-
STATE.fflags->write(STATE.fflags->read() | softfloat_exceptionFlags); \
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} \
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softfloat_exceptionFlags = 0; })
214+
#define raise_fp_exceptions(flags) do { if (flags) STATE.fflags->write(STATE.fflags->read() | (flags)); } while (0);
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#define set_fp_exceptions \
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do { \
217+
raise_fp_exceptions(softfloat_exceptionFlags); \
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softfloat_exceptionFlags = 0; \
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} while (0);
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219221
#define sext32(x) ((sreg_t)(int32_t)(x))
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#define zext32(x) ((reg_t)(uint32_t)(x))

riscv/insns/fcvtmod_w_d.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,5 @@ if (exp == 0) {
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}
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WRITE_RD(sext32(frac));
58-
STATE.fflags->write(STATE.fflags->read() |
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(inexact ? softfloat_flag_inexact : 0) |
58+
raise_fp_exceptions((inexact ? softfloat_flag_inexact : 0) |
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(invalid ? softfloat_flag_invalid : 0));

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