Add Smdbltrp

Author: ved-rivos

riscv/csrs.h

@@ -684,7 +684,7 @@ class dcsr_csr_t: public csr_t {
   dcsr_csr_t(processor_t* const proc, const reg_t addr);
   virtual void verify_permissions(insn_t insn, bool write) const override;
   virtual reg_t read() const noexcept override;
-  void update_fields(const uint8_t cause, const reg_t prv,
+  void update_fields(const uint8_t cause, const uint8_t ext_cause, const reg_t prv,
                      const bool v, const elp_t pelp) noexcept;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
@@ -699,6 +699,8 @@ class dcsr_csr_t: public csr_t {
   bool halt;
   bool v;
   uint8_t cause;
+  uint8_t ext_cause;
+  bool cetrig;
   elp_t pelp;
 };
 

riscv/encoding.h

@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (c55d30f)
+ * https://github.com/riscv/riscv-opcodes (23a394b)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -110,6 +110,9 @@
 #define DCSR_CAUSE_STEP     4
 #define DCSR_CAUSE_HALT     5
 #define DCSR_CAUSE_GROUP    6
+#define DCSR_CAUSE_EXTCAUSE 7
+
+#define DCSR_EXTCAUSE_CRITERR 0
 
 #define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
 #define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))

riscv/isa_parser.h

@@ -81,6 +81,7 @@ typedef enum {
   EXT_SSQOSID,
   EXT_ZICFILP,
   EXT_ZICFISS,
+  EXT_SMDBLTRP,
   NUM_ISA_EXTENSIONS
 } isa_extension_t;
 

riscv/processor.h

@@ -189,6 +189,7 @@ struct state_t
   int last_inst_flen;
 
   elp_t elp;
+  bool critical_error;
 };
 
 class opcode_cache_entry_t {
@@ -401,7 +402,7 @@ class processor_t : public abstract_device_t
   void register_insn(insn_desc_t, bool);
   int paddr_bits();
 
-  void enter_debug_mode(uint8_t cause);
+  void enter_debug_mode(uint8_t cause, uint8_t ext_cause);
 
   void debug_output_log(std::stringstream *s); // either output to interactive user or write to log file