cosim: fix right shift on neg number and remove redundant mask

referece from:  ISO C99 (6.5.7/4)
"The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated
 bits are filled with zeros. If E1 has an unsigned type, the value of the
 result is E1 × 2E2, reduced modulo one more than the maximum value
 representable in the result type. If E1 has a signed type and
 nonnegative value, and E1 × 2E2 is representable in the result type,
 then that is the resulting value; otherwise, the behavior is undefined."

list the affectections.  X means it is problematic and fixed by change

                      operand type     /   redundant mask
1. vsll.v[vxi]  ->        X                    X
2. vsra.v[vxi]  ->        O                    O
3. vsrl.v[vxi]  ->        O                    X
4. vwsll.v[vxi] ->        O                    O
5. vnsrl.w[vxi] ->        O                    O
6. vnsra.w[vxi] ->        O                    X
7. vssrl.v[vxi] ->        O                    X
7. vssra.v[vxi] ->        O                    X

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Author: chihminchao

riscv/insns/vnsra_wi.h

@@ -1,5 +1,5 @@
 // vnsra.vi vd, vs2, zimm5
 VI_VI_LOOP_NSHIFT
 ({
-  vd = vs2 >> (zimm5 & (sew * 2 - 1) & 0x1f);
+  vd = vs2 >> (zimm5 & (sew * 2 - 1));
 })

riscv/insns/vsll_vi.h

@@ -1,5 +1,5 @@
 // vsll.vi  vd, vs2, zimm5
-VI_VI_LOOP
+VI_VI_ULOOP
 ({
-  vd = vs2 << (simm5 & (sew - 1) & 0x1f);
+  vd = vs2 << (zimm5 & (sew - 1));
 })

riscv/insns/vsll_vv.h

@@ -1,5 +1,5 @@
 // vsll
-VI_VV_LOOP
+VI_VV_ULOOP
 ({
   vd = vs2 << (vs1 & (sew - 1));
 })

riscv/insns/vsll_vx.h

@@ -1,5 +1,5 @@
 // vsll
-VI_VX_LOOP
+VI_VX_ULOOP
 ({
   vd = vs2 << (rs1 & (sew - 1));
 })

riscv/insns/vsrl_vi.h

@@ -1,5 +1,5 @@
 // vsrl.vi vd, vs2, zimm5
 VI_VI_ULOOP
 ({
-  vd = vs2 >> (zimm5 & (sew - 1) & 0x1f);
+  vd = vs2 >> (zimm5 & (sew - 1));
 })

riscv/insns/vssra_vi.h

@@ -2,7 +2,7 @@
 VI_VI_LOOP
 ({
   VRM xrm = P.VU.get_vround_mode();
-  int sh = simm5 & (sew - 1) & 0x1f;
+  int sh = simm5 & (sew - 1);
   int128_t val = vs2;
 
   INT_ROUNDING(val, xrm, sh);

riscv/insns/vssrl_vi.h

@@ -2,7 +2,7 @@
 VI_VI_ULOOP
 ({
   VRM xrm = P.VU.get_vround_mode();
-  int sh = zimm5 & (sew - 1) & 0x1f;
+  int sh = zimm5 & (sew - 1);
   uint128_t val = vs2;
 
   INT_ROUNDING(val, xrm, sh);