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Remove all --varch parsing
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9 files changed

+1
-93
lines changed

9 files changed

+1
-93
lines changed

.github/workflows/debug-smoke.yml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ jobs:
4747
run: |
4848
git clone --recurse-submodules https://github.com/riscv-software-src/riscv-tests.git
4949
cd riscv-tests
50-
git checkout bd0a19c136927eaa3b7296a591a896c141affb6b
50+
git checkout 00ab5f0dd4cf56b5a0551bc5adedf60c765d0c66
5151
5252
- name: Run Tests
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run: |

config.h.in

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,6 @@
1212
/* Default value for --priv switch */
1313
#undef DEFAULT_PRIV
1414

15-
/* Default value for --varch switch */
16-
#undef DEFAULT_VARCH
17-
1815
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
1916
#undef DISASM_ENABLED
2017

configure

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -739,7 +739,6 @@ with_boost_asio
739739
with_boost_regex
740740
with_isa
741741
with_priv
742-
with_varch
743742
with_target
744743
enable_dual_endian
745744
'
@@ -1407,8 +1406,6 @@ Optional Packages:
14071406
--with-isa=RV64IMAFDC_zicntr_zihpm
14081407
Sets the default RISC-V ISA
14091408
--with-priv=MSU Sets the default RISC-V privilege modes supported
1410-
--with-varch=vlen:128,elen:64
1411-
Sets the default vector config
14121409
--with-target=riscv64-unknown-elf
14131410
Sets the default target config
14141411
@@ -6593,20 +6590,6 @@ fi
65936590

65946591

65956592

6596-
# Check whether --with-varch was given.
6597-
if test ${with_varch+y}
6598-
then :
6599-
withval=$with_varch;
6600-
printf "%s\n" "#define DEFAULT_VARCH \"$withval\"" >>confdefs.h
6601-
6602-
else $as_nop
6603-
6604-
printf "%s\n" "#define DEFAULT_VARCH \"vlen:128,elen:64\"" >>confdefs.h
6605-
6606-
fi
6607-
6608-
6609-
66106593
# Check whether --with-target was given.
66116594
if test ${with_target+y}
66126595
then :

riscv/cfg.cc

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,6 @@ cfg_t::cfg_t()
3535
bootargs = nullptr;
3636
isa = DEFAULT_ISA;
3737
priv = DEFAULT_PRIV;
38-
varch = DEFAULT_VARCH;
3938
misaligned = false;
4039
endianness = endianness_little;
4140
pmpregions = 16;

riscv/cfg.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,6 @@ class cfg_t
6767
const char * bootargs;
6868
const char * isa;
6969
const char * priv;
70-
const char * varch;
7170
bool misaligned;
7271
endianness_t endianness;
7372
reg_t pmpregions;

riscv/processor.cc

Lines changed: 0 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -105,29 +105,13 @@ static void bad_option_string(const char *option, const char *value,
105105
abort();
106106
}
107107

108-
static void bad_varch_string(const char* varch, const char *msg)
109-
{
110-
bad_option_string("--varch", varch, msg);
111-
}
112-
113108
static std::string get_string_token(std::string str, const char delimiter, size_t& pos)
114109
{
115110
size_t _pos = pos;
116111
while (pos < str.length() && str[pos] != delimiter) ++pos;
117112
return str.substr(_pos, pos - _pos);
118113
}
119114

120-
static int get_int_token(std::string str, const char delimiter, size_t& pos)
121-
{
122-
size_t _pos = pos;
123-
while (pos < str.length() && str[pos] != delimiter) {
124-
if (!isdigit(str[pos]))
125-
bad_varch_string(str.c_str(), "Unsupported value"); // An integer is expected
126-
++pos;
127-
}
128-
return (pos == _pos) ? 0 : stoi(str.substr(_pos, pos - _pos));
129-
}
130-
131115
static bool check_pow2(int val)
132116
{
133117
return ((val & (val - 1))) == 0;
@@ -141,51 +125,6 @@ static std::string strtolower(const char* str)
141125
return res;
142126
}
143127

144-
void processor_t::parse_varch_string(const char* s)
145-
{
146-
std::string str = strtolower(s);
147-
size_t pos = 0;
148-
size_t len = str.length();
149-
int vlen = 0;
150-
int elen = 0;
151-
int vstart_alu = 0;
152-
153-
while (pos < len) {
154-
std::string attr = get_string_token(str, ':', pos);
155-
156-
++pos;
157-
158-
if (attr == "vlen")
159-
vlen = get_int_token(str, ',', pos);
160-
else if (attr == "elen")
161-
elen = get_int_token(str, ',', pos);
162-
else if (attr == "vstartalu")
163-
vstart_alu = get_int_token(str, ',', pos);
164-
else
165-
bad_varch_string(s, "Unsupported token");
166-
167-
++pos;
168-
}
169-
170-
// The integer should be the power of 2
171-
if (!check_pow2(vlen) || !check_pow2(elen)) {
172-
bad_varch_string(s, "The integer value should be the power of 2");
173-
}
174-
175-
/* Vector spec requirements. */
176-
if (vlen < elen)
177-
bad_varch_string(s, "vlen must be >= elen");
178-
179-
/* spike requirements. */
180-
if (vlen > 4096)
181-
bad_varch_string(s, "vlen must be <= 4096");
182-
183-
VU.VLEN = vlen;
184-
VU.ELEN = elen;
185-
VU.vlenb = vlen / 8;
186-
VU.vstart_alu = vstart_alu;
187-
}
188-
189128
static int xlen_to_uxl(int xlen)
190129
{
191130
if (xlen == 32)

riscv/processor.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -410,7 +410,6 @@ class processor_t : public abstract_device_t
410410
friend class plic_t;
411411
friend class extension_t;
412412

413-
void parse_varch_string(const char*);
414413
void parse_priv_string(const char*);
415414
void build_opcode_map();
416415
void register_base_instructions();

riscv/riscv.ac

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -20,12 +20,6 @@ AC_ARG_WITH(priv,
2020
AC_DEFINE_UNQUOTED([DEFAULT_PRIV], "$withval", [Default value for --priv switch]),
2121
AC_DEFINE_UNQUOTED([DEFAULT_PRIV], "MSU", [Default value for --priv switch]))
2222

23-
AC_ARG_WITH(varch,
24-
[AS_HELP_STRING([--with-varch=vlen:128,elen:64],
25-
[Sets the default vector config])],
26-
AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "$withval", [Default value for --varch switch]),
27-
AC_DEFINE([DEFAULT_VARCH], ["vlen:128,elen:64"], [Default value for --varch switch]))
28-
2923
AC_ARG_WITH(target,
3024
[AS_HELP_STRING([--with-target=riscv64-unknown-elf],
3125
[Sets the default target config])],

spike_main/spike.cc

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,6 @@ static void help(int exit_code = 1)
4545
fprintf(stderr, " --pmpregions=<n> Number of PMP regions [default 16]\n");
4646
fprintf(stderr, " --pmpgranularity=<n> PMP Granularity in bytes [default 4]\n");
4747
fprintf(stderr, " --priv=<m|mu|msu> RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV);
48-
fprintf(stderr, " --varch=<name> RISC-V Vector uArch string [default %s]\n", DEFAULT_VARCH);
4948
fprintf(stderr, " --pc=<address> Override ELF entry point\n");
5049
fprintf(stderr, " --hartids=<a,b,...> Explicitly specify hartids, default is 0,1,...\n");
5150
fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
@@ -404,7 +403,6 @@ int main(int argc, char** argv)
404403
parser.option(0, "pmpregions", 1, [&](const char* s){cfg.pmpregions = atoul_safe(s);});
405404
parser.option(0, "pmpgranularity", 1, [&](const char* s){cfg.pmpgranularity = atoul_safe(s);});
406405
parser.option(0, "priv", 1, [&](const char* s){cfg.priv = s;});
407-
parser.option(0, "varch", 1, [&](const char* s){cfg.varch = s;});
408406
parser.option(0, "device", 1, device_parser);
409407
parser.option(0, "extension", 1, [&](const char* s){extensions.push_back(find_extension(s));});
410408
parser.option(0, "dump-dts", 0, [&](const char UNUSED *s){dump_dts = true;});

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