Separate RV32 and RV64 C instructions into separate files

aswaterman · aswaterman · commit 0325be55596b · 2024-06-11T13:51:14.000-07:00
diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
@@ -1,8 +1,3 @@
-if (xlen == 32) {
-  require_extension(EXT_ZCF);
-  require_fp;
-  WRITE_RVC_FRS2S(f32(MMU.load<uint32_t>(RVC_RS1S + insn.rvc_lw_imm())));
-} else { // c.ld
-  require_extension(EXT_ZCA);
-  WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));
-}
+require_extension(EXT_ZCF);
+require_fp;
+WRITE_RVC_FRS2S(f32(MMU.load<uint32_t>(RVC_RS1S + insn.rvc_lw_imm())));
diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h
@@ -1,9 +1,3 @@
-if (xlen == 32) {
-  require_extension(EXT_ZCF);
-  require_fp;
-  WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm())));
-} else { // c.ldsp
-  require_extension(EXT_ZCA);
-  require(insn.rvc_rd() != 0);
-  WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
-}
+require_extension(EXT_ZCF);
+require_fp;
+WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm())));
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
@@ -1,8 +1,3 @@
-if (xlen == 32) {
-  require_extension(EXT_ZCF);
-  require_fp;
-  MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]);
-} else { // c.sd
-  require_extension(EXT_ZCA);
-  MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
-}
+require_extension(EXT_ZCF);
+require_fp;
+MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]);
diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
@@ -1,8 +1,3 @@
-if (xlen == 32) {
-  require_extension(EXT_ZCF);
-  require_fp;
-  MMU.store<uint32_t>(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]);
-} else { // c.sdsp
-  require_extension(EXT_ZCA);
-  MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
-}
+require_extension(EXT_ZCF);
+require_fp;
+MMU.store<uint32_t>(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]);
diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZCA);
+WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));
diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h
@@ -0,0 +1,3 @@
+require_extension(EXT_ZCA);
+require(insn.rvc_rd() != 0);
+WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZCA);
+MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
@@ -0,0 +1,2 @@
+require_extension(EXT_ZCA);
+MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
diff --git a/riscv/overlap_list.h b/riscv/overlap_list.h
@@ -1,3 +1,9 @@
+// these overlap c.ld[sp]/c.sd[sp]
+DECLARE_OVERLAP_INSN(c_flw, EXT_ZCF)
+DECLARE_OVERLAP_INSN(c_flwsp, EXT_ZCF)
+DECLARE_OVERLAP_INSN(c_fsw, EXT_ZCF)
+DECLARE_OVERLAP_INSN(c_fswsp, EXT_ZCF)
+
 // these overlap c.fsdsp
 DECLARE_OVERLAP_INSN(cm_push, EXT_ZCMP)
 DECLARE_OVERLAP_INSN(cm_pop, EXT_ZCMP)
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
@@ -182,6 +182,8 @@ riscv_insn_ext_c = \
 	c_jr \
 	c_li \
 	c_lui \
+	c_ld \
+	c_ldsp \
 	c_lw \
 	c_lwsp \
 	c_mv \
@@ -191,6 +193,8 @@ riscv_insn_ext_c = \
 	c_srli \
 	c_sub \
 	c_subw \
+	c_sd \
+	c_sdsp \
 	c_sw \
 	c_swsp \
 	c_xor \

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+require_extension(EXT_ZCA);`
	`2`	`+WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm()));`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,3 @@`
	`1`	`+require_extension(EXT_ZCA);`
	`2`	`+require(insn.rvc_rd() != 0);`
	`3`	`+WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+require_extension(EXT_ZCA);`
	`2`	`+MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+require_extension(EXT_ZCA);`
	`2`	`+MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);`