Update e310x with latest svd2rust version

Author: romancardenas

e310x/CHANGELOG.md

@@ -8,8 +8,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 ### Changed
-- Bump MSRV to 1.72.0 to ensure a correct behavior of portable-atomic
-- Regenerate code with `svd2rust` v0.33.4
+
+- Now CLINT and PLIC are provided by `riscv-peripheral` 0.2
+- Adapt crate to work with `riscv` 0.12 and `riscv-rt` 0.13
+- Bump MSRV to 1.76.0 to ensure a correct behavior of portable-atomic
+- Regenerate code with `svd2rust` 8b809ac2c1e1a13f30af59ee41f4d66a4995d625 (unreleased)
 
 ## [v0.11.0]
 

e310x/Cargo.toml

@@ -1,21 +1,25 @@
 [package]
 name = "e310x"
-version = "0.11.0"
+version = "0.12.0"
 repository = "https://github.com/riscv-rust/e310x"
 authors = ["David Craven <david@craven.ch>", "The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "With svd2rust generated peripherals for Freedom E310 MCU's."
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
-rust-version = "1.72"
+rust-version = "1.76"
 edition = "2021"
 
 [dependencies]
-critical-section = { version = "1.1.3", optional = true }
+critical-section = { version = "1.2.0", optional = true }
+riscv = "0.12.0"
+riscv-peripheral = "0.2.0"
+riscv-rt = { version = "0.13.0", features = ["no-interrupts"], optional = true }
 vcell = "0.1.3"
 
 [features]
-rt = []
+rt = ["riscv-rt"]
+v-trap = ["rt", "riscv-rt/v-trap"]
 g002 = []
 
 [package.metadata.docs.rs]

e310x/device.x

@@ -3,6 +3,14 @@ MEMORY
     RAM : ORIGIN = 0x80000000, LENGTH = 16K
 }
 
+/* Core interrupt sources and trap handlers */
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(_start_MachineSoft_trap = _start_DefaultHandler_trap);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(_start_MachineTimer_trap = _start_DefaultHandler_trap);
+PROVIDE(MachineExternal = DefaultHandler);
+PROVIDE(_start_MachineExternal_trap = _start_DefaultHandler_trap);
+/* External interrupt sources */
 PROVIDE(WATCHDOG = DefaultHandler);
 PROVIDE(RTC = DefaultHandler);
 PROVIDE(UART0 = DefaultHandler);

e310x/settings.yaml

@@ -0,0 +1,52 @@
+riscv_config:
+  core_interrupts:
+    - name: "MachineSoft"
+      value: 3
+      description: "Machine Software Interrupt"
+    - name: "MachineTimer"
+      value: 7
+      description: "Machine Timer Interrupt"
+    - name: "MachineExternal"
+      value: 11
+      description: "Machine External Interrupt"
+
+  priorities:
+    - name: "P0"
+      value: 0
+      description: "Priority level 0"
+    - name: "P1"
+      value: 1
+      description: "Priority level 1"
+    - name: "P2"
+      value: 2
+      description: "Priority level 2"
+    - name: "P3"
+      value: 3
+      description: "Priority level 3"
+    - name: "P4"
+      value: 4
+      description: "Priority level 4"
+    - name: "P5"
+      value: 5
+      description: "Priority level 5"
+    - name: "P6"
+      value: 6
+      description: "Priority level 6"
+    - name: "P7"
+      value: 7
+      description: "Priority level 7"
+
+  harts:
+    - name: "H0"
+      value: 0
+      description: "Hart 0"
+
+  clint:
+    name: "CLINT"
+    freq: 32768
+    async_delay: false
+
+  plic:
+    name: "PLIC"
+    core_interrupt: "MachineExternal"
+    hart_id: "H0"

e310x/src/aonclk/lfrosccfg.rs

@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn div(&mut self) -> DivW<LfrosccfgSpec> {
         DivW::new(self, 0)
     }
     #[doc = "Bits 16:20"]
     #[inline(always)]
-    #[must_use]
     pub fn trim(&mut self) -> TrimW<LfrosccfgSpec> {
         TrimW::new(self, 16)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> EnableW<LfrosccfgSpec> {
         EnableW::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ready(&mut self) -> ReadyW<LfrosccfgSpec> {
         ReadyW::new(self, 31)
     }