RISC-V peripheral rework

Author: romancardenas

e310x-hal/src/clock.rs

@@ -1,6 +1,6 @@
 //! Clock configuration
 use crate::time::Hertz;
-use e310x::{Aonclk as AONCLK, Prci as PRCI, CLINT};
+use e310x::{Aonclk as AONCLK, Clint, Prci as PRCI};
 use riscv::interrupt;
 use riscv::register::mcycle;
 
@@ -290,7 +290,7 @@ impl CoreClk {
         // Need to wait 100 us
         // RTC is running at 32kHz.
         // So wait 4 ticks of RTC.
-        let mtime = CLINT::mtimer().mtime;
+        let mtime = unsafe { Clint::steal() }.mtimer().mtime();
         let time = mtime.read() + 4;
         while mtime.read() < time {}
         // Now it is safe to check for PLL Lock
@@ -384,7 +384,7 @@ impl Clocks {
 
     /// Measure the coreclk frequency by counting the number of aonclk ticks.
     fn _measure_coreclk(&self, min_ticks: u64) -> Hertz {
-        let mtime = CLINT::mtimer().mtime;
+        let mtime = unsafe { Clint::steal() }.mtimer().mtime();
         interrupt::free(|| {
             // Don't start measuring until we see an mtime tick
             while mtime.read() == mtime.read() {}

e310x-hal/src/core/counters.rs

@@ -60,7 +60,7 @@ pub struct PerformanceCounters {
 }
 
 impl PerformanceCounters {
-    pub(crate) fn new() -> Self {
+    pub(crate) const fn new() -> Self {
         Self {
             mcycle: MCYCLE,
             minstret: MINSTRET,

e310x-hal/src/core/mod.rs

@@ -2,17 +2,23 @@
 
 pub mod counters;
 
-pub use e310x::{CLINT, PLIC};
+use e310x::{Clint, Plic};
 
 /// Core peripherals
 pub struct CorePeripherals {
+    /// Core Local Interruptor (CLINT)
+    pub clint: Clint,
+    /// Platform-Level Interrupt Controller (PLIC)
+    pub plic: Plic,
     /// Performance counters
     pub counters: counters::PerformanceCounters,
 }
 
 impl CorePeripherals {
-    pub(crate) fn new() -> Self {
+    pub(crate) const fn new(clint: Clint, plic: Plic) -> Self {
         Self {
+            clint,
+            plic,
             counters: counters::PerformanceCounters::new(),
         }
     }
@@ -23,6 +29,6 @@ impl CorePeripherals {
     ///
     /// Using this function may break the guarantees of the singleton pattern.
     pub unsafe fn steal() -> Self {
-        Self::new()
+        Self::new(Clint::steal(), Plic::steal())
     }
 }

e310x-hal/src/delay.rs

@@ -1,7 +1,7 @@
 //! # Delays
 
 use crate::clock::Clocks;
-use e310x::CLINT;
+use e310x::Clint;
 use embedded_hal::delay::DelayNs;
 use riscv::register::mip;
 
@@ -22,7 +22,7 @@ impl DelayNs for Delay {
     fn delay_ns(&mut self, ns: u32) {
         let ticks = (ns as u64) * TICKS_PER_SECOND / 1_000_000_000;
 
-        let mtime = CLINT::mtimer().mtime;
+        let mtime = unsafe { Clint::steal() }.mtimer().mtime();
         let t = mtime.read() + ticks;
         while mtime.read() < t {}
     }
@@ -45,12 +45,13 @@ impl Sleep {
 impl DelayNs for Sleep {
     fn delay_ns(&mut self, ns: u32) {
         let ticks = (ns as u64) * u64::from(self.clock_freq) / 1_000_000_000;
-        let t = CLINT::mtimer().mtime.read() + ticks;
+        let clint = unsafe { e310x::Clint::steal() };
+        let t = clint.mtimer().mtime().read() + ticks;
 
-        CLINT::mtimecmp0().write(t);
+        clint.mtimecmp0().write(t);
 
         // Enable timer interrupt
-        unsafe { CLINT::mtimer_enable() };
+        unsafe { clint.mtimer().enable() };
 
         // Wait For Interrupt will put CPU to sleep until an interrupt hits
         // in our case when internal timer mtime value >= mtimecmp value
@@ -66,6 +67,6 @@ impl DelayNs for Sleep {
         }
 
         // Clear timer interrupt
-        CLINT::mtimer_disable();
+        clint.mtimer().disable();
     }
 }

e310x-hal/src/device.rs

@@ -159,7 +159,7 @@ impl From<Peripherals> for DeviceResources {
         };
 
         DeviceResources {
-            core_peripherals: CorePeripherals::new(),
+            core_peripherals: CorePeripherals::new(p.clint, p.plic),
             peripherals,
             pins: p.gpio0.into(),
         }

e310x/Cargo.toml

@@ -12,9 +12,12 @@ edition = "2021"
 
 [dependencies]
 critical-section = { version = "1.2.0", optional = true }
-riscv = "0.13.0"
-riscv-peripheral = "0.2.0"
-riscv-rt = { version = "0.14.0", features = ["no-interrupts"], optional = true }
+riscv = { git = "https://github.com/rust-embedded/riscv.git", branch = "riscv-peripheral-rework" }
+riscv-peripheral = { git = "https://github.com/rust-embedded/riscv.git", branch = "riscv-peripheral-rework" }
+riscv-rt = { git = "https://github.com/rust-embedded/riscv.git", branch = "riscv-peripheral-rework", features = ["no-interrupts"], optional = true }
+# riscv = "0.13.0"
+# riscv-peripheral = "0.2.0"
+# riscv-rt = { version = "0.14.0", features = ["no-interrupts"], optional = true }
 vcell = "0.1.3"
 
 [features]

e310x/settings.yaml

@@ -43,8 +43,7 @@ riscv_config:
 
   clint:
     name: "CLINT"
-    freq: 32768
-    async_delay: false
+    mtime_freq: 32768
 
   plic:
     name: "PLIC"

e310x/src/interrupt.rs

@@ -168,8 +168,9 @@ pub enum ExternalInterrupt {
 }
 #[cfg(feature = "rt")]
 #[riscv_rt::core_interrupt(CoreInterrupt::MachineExternal)]
-fn plic_handler() {
-    let claim = crate::PLIC::ctx(Hart::H0).claim();
+unsafe fn plic_handler() {
+    let plic = unsafe { crate::Plic::steal() };
+    let claim = plic.ctx(Hart::H0).claim();
     if let Some(s) = claim.claim::<ExternalInterrupt>() {
         unsafe { _dispatch_external_interrupt(s.number()) }
         claim.complete(s);

e310x/src/lib.rs

@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for FE310 microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for FE310 microcontrollers (generated using svd2rust v0.36.1 (7a01f7c 2025-05-24))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![no_std]
@@ -9,8 +9,46 @@ use generic::*;
 pub mod generic;
 #[doc = r" Interrupt numbers, priority levels, and HART IDs."]
 pub mod interrupt;
-riscv_peripheral :: clint_codegen ! (base 0x2000000 , freq 32768 , mtimecmps [mtimecmp0 = (crate :: interrupt :: Hart :: H0 , "[0](crate::interrupt::Hart::H0)")] , msips [msip0 = (crate :: interrupt :: Hart :: H0 , "[0](crate::interrupt::Hart::H0)")] ,);
-riscv_peripheral :: plic_codegen ! (base 0xC000000 , ctxs [ctx0 = (crate :: interrupt :: Hart :: H0 , "[0](crate::interrupt::Hart::H0)")] ,);
+riscv_peripheral :: clint_codegen ! (Clint , base 0x2000000 , mtime_freq 32768 , harts [crate :: interrupt :: Hart :: H0 => 0]);
+impl Clint {
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    #[inline]
+    pub unsafe fn steal() -> Self {
+        Self::new()
+    }
+}
+riscv_peripheral :: plic_codegen ! (Plic , base 0xC000000 , harts [crate :: interrupt :: Hart :: H0 => 0]);
+impl Plic {
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    #[inline]
+    pub unsafe fn steal() -> Self {
+        Self::new()
+    }
+}
 #[doc = "Watchdog"]
 pub type Wdog = crate::Periph<wdog::RegisterBlock, 0x1000_0000>;
 impl core::fmt::Debug for Wdog {
@@ -172,6 +210,10 @@ static mut DEVICE_PERIPHERALS: bool = false;
 #[doc = r" All the peripherals."]
 #[allow(non_snake_case)]
 pub struct Peripherals {
+    #[doc = "CLINT"]
+    pub clint: Clint,
+    #[doc = "PLIC"]
+    pub plic: Plic,
     #[doc = "WDOG"]
     pub wdog: Wdog,
     #[doc = "RTC"]
@@ -229,6 +271,8 @@ impl Peripherals {
     pub unsafe fn steal() -> Self {
         DEVICE_PERIPHERALS = true;
         Peripherals {
+            clint: Clint::steal(),
+            plic: Plic::steal(),
             wdog: Wdog::steal(),
             rtc: Rtc::steal(),
             aonclk: Aonclk::steal(),