Merge pull request #24 from riscv-rust/delay_reset

Fix delay0 and delay1 reset value

Author: Disasm

e310x.svd

@@ -1836,6 +1836,7 @@
           <name>delay0</name>
           <description>Delay Control 0 Register</description>
           <addressOffset>0x28</addressOffset>
+          <resetValue>0x00010001</resetValue>
           <fields>
             <field>
               <name>sckcs</name>
@@ -1853,6 +1854,7 @@
           <name>delay1</name>
           <description>Delay Control 1 Register</description>
           <addressOffset>0x2C</addressOffset>
+          <resetValue>0x00000001</resetValue>
           <fields>
             <field>
               <name>interxfr</name>

src/common/qspi0/delay0.rs

@@ -129,10 +129,10 @@ impl crate::Readable for DELAY0_SPEC {
 impl crate::Writable for DELAY0_SPEC {
     type Writer = W;
 }
-#[doc = "`reset()` method sets delay0 to value 0"]
+#[doc = "`reset()` method sets delay0 to value 0x0001_0001"]
 impl crate::Resettable for DELAY0_SPEC {
     #[inline(always)]
     fn reset_value() -> Self::Ux {
-        0
+        0x0001_0001
     }
 }

src/common/qspi0/delay1.rs

@@ -129,10 +129,10 @@ impl crate::Readable for DELAY1_SPEC {
 impl crate::Writable for DELAY1_SPEC {
     type Writer = W;
 }
-#[doc = "`reset()` method sets delay1 to value 0"]
+#[doc = "`reset()` method sets delay1 to value 0x01"]
 impl crate::Resettable for DELAY1_SPEC {
     #[inline(always)]
     fn reset_value() -> Self::Ux {
-        0
+        0x01
     }
 }