Adapt e310x-hal to new version of e310x

Author: romancardenas

.github/workflows/changelog.yaml

@@ -19,6 +19,8 @@ jobs:
           filters: |
             e310x:
               - 'e310x/**'
+            e310x-hal:
+              - 'e310x-hal/**'
 
       - name: Check for CHANGELOG.md (e310x)
         if: steps.changes.outputs['e310x'] == 'true'
@@ -27,3 +29,12 @@ jobs:
           changeLogPath: ./e310x/CHANGELOG.md
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the e310x/CHANGELOG.md file.'
+      
+      - name: Check for CHANGELOG.md (e310x-hal)
+        if: steps.changes.outputs['e310x-hal'] == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: ./e310x-hal/CHANGELOG.md
+          skipLabels: 'skip changelog'
+          missingUpdateErrorMessage: 'Please add a changelog entry in the e310x-hal/CHANGELOG.md file.'
+  

.github/workflows/e310x-hal.yaml

@@ -0,0 +1,51 @@
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+  merge_group:
+
+name: Build check (e310x-hal)
+
+jobs:
+  # We check that the crate builds and links for all the toolchains and targets.
+  build-riscv:
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.65.0
+        toolchain: [ stable, nightly, 1.65.0 ]
+        target:
+          - riscv32imc-unknown-none-elf
+          - riscv32imac-unknown-none-elf # TODO e310x is not a purely IMAC core
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental || false }}
+    steps:
+    - uses: actions/checkout@v4
+    - name: Update Rust toolchain
+      run: rustup update ${{ matrix.toolchain }} && rustup default ${{ matrix.toolchain }}
+    - name: Install Rust target
+      run: rustup target install ${{ matrix.target }}
+    - name: Build (no features)
+      run: cargo build --package e310x-hal --target ${{ matrix.target }}
+    - name: Build (all features)
+      run: cargo build --package e310x-hal --target ${{ matrix.target }} --all-features
+
+  # On MacOS and Ubuntu, we at least make sure that the crate builds and links.
+  # On Windows, linking fails when the rt feature is enabled.
+  build-others:
+    strategy:
+      matrix:
+        os: [ macos-latest, ubuntu-latest ]
+    runs-on: ${{ matrix.os }}
+    steps:
+      - uses: actions/checkout@v4
+      - name: Update Rust toolchain
+        run: rustup update stable && rustup default stable
+      - name: Build (no features)
+        run: cargo test --package e310x-hal
+      - name: Build (all features)
+        run: cargo test --package e310x-hal --all-features
+  

.gitignore

@@ -1,2 +1,3 @@
 Cargo.lock
-target/
+target/
+.vscode/

.travis.yml

@@ -2,4 +2,5 @@
 resolver = "2"
 members = [
     "e310x",
+    "e310x-hal",
 ]

Cargo.toml

@@ -3,6 +3,7 @@
 This repository contains various crates useful for writing Rust programs on E310x microcontrollers:
 
 * [`e310x`]: Peripheral Access Crate (PAC) for E310x chips.
+* [`e310x-hal`]: HAL for the E310x family of microcontrollers.
 
 This project is developed and maintained by the [RISC-V team][team].
 

README.md

@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+- Update `e310x` dependency and adapt code
+- Bump MSRV to 1.65.0 (check Cargo.toml)
 - Use `portable-atomic` to allow builds on `riscv32imc-unknown-none-elf`` targets when needed.
 
 ## [v0.10.0] - 2023-03-28

e310x-hal/CHANGELOG.md

@@ -2,19 +2,19 @@
 name = "e310x-hal"
 version = "0.11.0"
 authors = ["David Craven <david@craven.ch>"]
-repository = "https://github.com/riscv-rust/e310x-hal"
+repository = "https://github.com/riscv-rust/e310x"
 categories = ["embedded", "hardware-support", "no-std"]
 description = "HAL for the E310x family of microcontrollers."
 keywords = ["riscv", "e310", "hal"]
 license = "ISC"
-edition = "2018"
-rust-version = "1.59"
+edition = "2021"
+rust-version = "1.65"
 
 [dependencies]
 embedded-hal = { version = "0.2.6", features = ["unproven"] }
 nb = "1.0.0"
 riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }
-e310x = { version = "0.11.0", features = ["rt", "critical-section"] }
+e310x = { path = "../e310x", version = "0.11.0", features = ["rt", "critical-section"] }
 
 [target.'cfg(not(target_has_atomic = "32"))'.dependencies]
 portable-atomic = { version = "1.4", default-features = false, features = ["unsafe-assume-single-core"] }

e310x-hal/Cargo.toml

@@ -1,7 +1,7 @@
 //! Clock configuration
 use crate::core::clint::MTIME;
 use crate::time::Hertz;
-use e310x::{AONCLK, PRCI};
+use e310x::{Aonclk as AONCLK, Prci as PRCI};
 use riscv::interrupt;
 use riscv::register::mcycle;
 
@@ -72,10 +72,10 @@ impl CoreClk {
         // Assume `psdclkbypass_n` is not used
 
         // Temporarily switch to the internal oscillator
-        let prci = unsafe { &*PRCI::ptr() };
+        let prci = unsafe { PRCI::steal() };
         let hfrosc_freq = self.configure_hfrosc();
         // Switch to HFROSC, bypass PLL
-        prci.pllcfg
+        prci.pllcfg()
             .modify(|_, w| w.sel().bit(false).bypass().bit(true));
 
         if let Some(freq) = self.hfxosc {
@@ -87,27 +87,27 @@ impl CoreClk {
 
     /// Configures clock generation system with external oscillator
     fn configure_with_external(self, source_freq: Hertz) -> Hertz {
-        let prci = unsafe { &*PRCI::ptr() };
+        let prci = unsafe { PRCI::steal() };
 
         // Enable HFXOSC
-        prci.hfxosccfg.write(|w| w.enable().bit(true));
+        prci.hfxosccfg().write(|w| w.enable().bit(true));
 
         // Wait for HFXOSC to stabilize
-        while !prci.hfxosccfg.read().ready().bit_is_set() {}
+        while !prci.hfxosccfg().read().ready().bit_is_set() {}
 
         // Select HFXOSC as pllref
-        prci.pllcfg.modify(|_, w| w.refsel().bit(true));
+        prci.pllcfg().modify(|_, w| w.refsel().bit(true));
 
         let freq;
         if source_freq.0 == self.coreclk.0 {
             // Use external oscillator with bypassed PLL
             freq = source_freq;
 
             // Bypass PLL
-            prci.pllcfg.modify(|_, w| w.bypass().bit(true));
+            prci.pllcfg().modify(|_, w| w.bypass().bit(true));
 
             // Bypass divider
-            prci.plloutdiv.write(|w| w.divby1().bit(true));
+            prci.plloutdiv().write(|w| w.divby1().bit(true));
         } else {
             // Use external oscillator with PLL
 
@@ -116,57 +116,57 @@ impl CoreClk {
         }
 
         // Switch to PLL
-        prci.pllcfg.modify(|_, w| w.sel().bit(true));
+        prci.pllcfg().modify(|_, w| w.sel().bit(true));
 
         // Disable HFROSC to save power
-        prci.hfrosccfg.write(|w| w.enable().bit(false));
+        prci.hfrosccfg().write(|w| w.enable().bit(false));
 
         freq
     }
 
     /// Configures clock generation system with internal oscillator
     fn configure_with_internal(self, hfrosc_freq: Hertz) -> Hertz {
-        let prci = unsafe { &*PRCI::ptr() };
+        let prci = unsafe { PRCI::steal() };
 
         let freq;
         if hfrosc_freq.0 == self.coreclk.0 {
             // Use internal oscillator with bypassed PLL
             freq = hfrosc_freq;
 
             // Switch to HFROSC, bypass PLL to save power
-            prci.pllcfg
+            prci.pllcfg()
                 .modify(|_, w| w.sel().bit(false).bypass().bit(true));
 
             //
-            prci.pllcfg.modify(|_, w| w.bypass().bit(true));
+            prci.pllcfg().modify(|_, w| w.bypass().bit(true));
         } else {
             // Use internal oscillator with PLL
 
             // Configure PLL and divider
             freq = self.configure_pll(hfrosc_freq, self.coreclk);
 
             // Switch to PLL
-            prci.pllcfg.modify(|_, w| w.sel().bit(true));
+            prci.pllcfg().modify(|_, w| w.sel().bit(true));
         }
 
         // Disable HFXOSC to save power
-        prci.hfxosccfg.write(|w| w.enable().bit(false));
+        prci.hfxosccfg().write(|w| w.enable().bit(false));
 
         freq
     }
 
     /// Configures internal high-frequency oscillator (`HFROSC`)
     fn configure_hfrosc(&self) -> Hertz {
-        let prci = unsafe { &*PRCI::ptr() };
+        let prci = unsafe { PRCI::steal() };
 
         // TODO: use trim value from OTP
 
         // Configure HFROSC to 13.8 MHz
-        prci.hfrosccfg
+        prci.hfrosccfg()
             .write(|w| unsafe { w.div().bits(4).trim().bits(16).enable().bit(true) });
 
         // Wait for HFROSC to stabilize
-        while !prci.hfrosccfg.read().ready().bit_is_set() {}
+        while !prci.hfrosccfg().read().ready().bit_is_set() {}
 
         Hertz(13_800_000)
     }
@@ -270,8 +270,8 @@ impl CoreClk {
         };
 
         // Configure PLL
-        let prci = unsafe { &*PRCI::ptr() };
-        prci.pllcfg.modify(|_, w| unsafe {
+        let prci = unsafe { PRCI::steal() };
+        prci.pllcfg().modify(|_, w| unsafe {
             w.pllr()
                 .bits(r)
                 .pllf()
@@ -283,7 +283,7 @@ impl CoreClk {
         });
 
         // Configure PLL Output Divider
-        prci.plloutdiv
+        prci.plloutdiv()
             .write(|w| unsafe { w.div().bits(divider_div as u8).divby1().bit(divider_bypass) });
 
         // Wait for PLL Lock
@@ -295,7 +295,7 @@ impl CoreClk {
         let time = mtime.mtime() + 4;
         while mtime.mtime() < time {}
         // Now it is safe to check for PLL Lock
-        while !prci.pllcfg.read().lock().bit_is_set() {}
+        while !prci.pllcfg().read().lock().bit_is_set() {}
 
         Hertz(divout_freq)
     }
@@ -318,13 +318,13 @@ impl AonClk {
 
     /// Freezes low-frequency clock configuration, making it effective
     pub(crate) fn freeze(self) -> Hertz {
-        let aonclk = unsafe { &*AONCLK::ptr() };
+        let aonclk = unsafe { AONCLK::steal() };
 
         if let Some(freq) = self.lfaltclk {
             // Use external oscillator.
 
             // Disable unused LFROSC to save power.
-            aonclk.lfrosccfg.write(|w| w.enable().bit(false));
+            aonclk.lfrosccfg().write(|w| w.enable().bit(false));
 
             freq
         } else {
@@ -334,14 +334,14 @@ impl AonClk {
             let div = 4; // LFROSC/5
 
             // Configure LFROSC
-            aonclk.lfrosccfg.write(|w| unsafe {
+            aonclk.lfrosccfg().write(|w| unsafe {
                 w.trim().bits(trim);
                 w.div().bits(div);
                 w.enable().bit(true)
             });
 
             // Wait for LFROSC to stabilize
-            while !aonclk.lfrosccfg.read().ready().bit_is_set() {}
+            while !aonclk.lfrosccfg().read().ready().bit_is_set() {}
 
             Hertz(32_768) // It's not so accurate: ≈30 kHz according to the datasheet
         }