Merge pull request #52 from riscv-rust/svdup

Release v0.10.0

Author: dkhayes117

CHANGELOG.md

@@ -7,12 +7,19 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-- Refactored `e310x-hal::spi` module, splitting the abstraction into `SpiBus` and `SpiExclusiveDevice/SpiSharedDevice` to allow multiple devices on a single SPI bus to co-exist
+## [v0.10.0] - 2023-03-28
+
+### Added
 - Added Pulse Width Modulation interface implementing `embedded_hal::Pwm`
-- Added `interrupt` module for vectored interrupt handlers.
-This module is only active if feature `virq` is selected.
-- Update `e310x` dependency to version 0.10
-- Update `riscv` dependency to version 0.8
+- Added `interrupt` module for vectored interrupt handlers. This module is only active if feature `virq` is selected.
+
+### Changed
+- Refactored `e310x-hal::spi` module, splitting the abstraction into `SpiBus` and `SpiExclusiveDevice/SpiSharedDevice` to allow multiple devices on a single SPI bus to co-exist
+- Update `e310x` dependency to version 0.11
+- Update `riscv` dependency to version 0.10
+
+### Removed
+- removed interrupt linking definitions, they are now provided by `e310x` via `svd2rust`
 
 ## [v0.9.4] - 2022-07-10
 

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "e310x-hal"
-version = "0.10.0"
+version = "0.11.0"
 authors = ["David Craven <david@craven.ch>"]
 repository = "https://github.com/riscv-rust/e310x-hal"
 categories = ["embedded", "hardware-support", "no-std"]
@@ -13,8 +13,8 @@ rust-version = "1.59"
 [dependencies]
 embedded-hal = { version = "0.2.6", features = ["unproven"] }
 nb = "1.0.0"
-riscv = "0.8.0"
-e310x = { version = "0.10.0", features = ["rt"] }
+riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }
+e310x = { version = "0.11.0", features = ["rt", "critical-section"] }
 
 [features]
 g002 = ["e310x/g002"]

build.rs

@@ -386,7 +386,7 @@ impl Clocks {
     /// Measure the coreclk frequency by counting the number of aonclk ticks.
     fn _measure_coreclk(&self, min_ticks: u64) -> Hertz {
         let mtime = MTIME;
-        interrupt::free(|_| {
+        interrupt::free(|| {
             // Don't start measuring until we see an mtime tick
             while mtime.mtime() == mtime.mtime() {}
 

fe310x-interrupt.x

@@ -2,21 +2,20 @@ use core::cell::RefCell;
 use core::ops::Deref;
 pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 use riscv::interrupt;
-use riscv::interrupt::Mutex;
 
 use super::{PinCS, PinsNoCS, SpiBus, SpiConfig, SpiSharedDevice, SpiX};
 
 /// Newtype for RefCell<Spi> locked behind a Mutex.
 /// Used to hold the [SpiBus] instance so it can be used for multiple [SpiSharedDevice] instances.
-pub struct SharedBus<SPI, PINS>(Mutex<RefCell<SpiBus<SPI, PINS>>>);
+pub struct SharedBus<SPI, PINS>(RefCell<SpiBus<SPI, PINS>>);
 
 impl<SPI, PINS> SharedBus<SPI, PINS>
 where
     SPI: SpiX,
     PINS: PinsNoCS<SPI>,
 {
     pub(crate) fn new(bus: SpiBus<SPI, PINS>) -> Self {
-        Self(Mutex::new(RefCell::new(bus)))
+        Self(RefCell::new(bus))
     }
 
     /// Create a new shared device on this SPI bus.
@@ -39,30 +38,30 @@ where
 {
     /// Set HOLD CS mode to per-frame operation, unless CSMODE is set to OFF
     pub fn start_frame(&mut self) {
-        interrupt::free(|cs| {
-            let mut bus = self.0.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.0.borrow_mut();
             bus.start_frame();
         });
     }
 
     /// Finishes transfer by deasserting CS (only for hardware-controlled CS)
     pub fn end_frame(&mut self) {
-        interrupt::free(|cs| {
-            let mut bus = self.0.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.0.borrow_mut();
             bus.end_frame();
         });
     }
 
     /// Releases the SPI peripheral and associated pins
     pub fn release(self) -> (SPI, PINS) {
-        let bus = self.0.into_inner().into_inner();
+        let bus = self.0.into_inner();
 
         (bus.spi, bus.pins)
     }
 }
 
 impl<SPI, PINS> Deref for SharedBus<SPI, PINS> {
-    type Target = Mutex<RefCell<SpiBus<SPI, PINS>>>;
+    type Target = RefCell<SpiBus<SPI, PINS>>;
 
     fn deref(&self) -> &Self::Target {
         &self.0

interrupts.x

@@ -49,8 +49,8 @@ where
     type Error = Infallible;
 
     fn read(&mut self) -> nb::Result<u8, Infallible> {
-        interrupt::free(|cs| {
-            let mut bus = self.bus.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.bus.borrow_mut();
 
             bus.configure(&self.config, Some(CS::CS_INDEX));
 
@@ -59,8 +59,8 @@ where
     }
 
     fn send(&mut self, byte: u8) -> nb::Result<(), Infallible> {
-        interrupt::free(|cs| {
-            let mut bus = self.bus.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.bus.borrow_mut();
 
             bus.configure(&self.config, Some(CS::CS_INDEX));
 
@@ -78,8 +78,8 @@ where
     type Error = Infallible;
 
     fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
-        interrupt::free(move |cs| {
-            let mut bus = self.bus.borrow(*cs).borrow_mut();
+        interrupt::free(move || {
+            let mut bus = self.bus.borrow_mut();
 
             bus.configure(&self.config, Some(CS::CS_INDEX));
 
@@ -101,8 +101,8 @@ where
     type Error = Infallible;
 
     fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
-        interrupt::free(|cs| {
-            let mut bus = self.bus.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.bus.borrow_mut();
 
             bus.configure(&self.config, Some(CS::CS_INDEX));
 
@@ -127,8 +127,8 @@ where
     where
         WI: IntoIterator<Item = u8>,
     {
-        interrupt::free(|cs| {
-            let mut bus = self.bus.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.bus.borrow_mut();
 
             bus.configure(&self.config, Some(CS::CS_INDEX));
 
@@ -150,8 +150,8 @@ where
     type Error = Infallible;
 
     fn exec<'op>(&mut self, operations: &mut [Operation<'op, u8>]) -> Result<(), Infallible> {
-        interrupt::free(|cs| {
-            let mut bus = self.bus.borrow(*cs).borrow_mut();
+        interrupt::free(|| {
+            let mut bus = self.bus.borrow_mut();
 
             bus.configure(&self.config, Some(CS::CS_INDEX));