Merge pull request #40 from riscv-rust/svd2rust-v0.36.1

Regenerate with svd2rust v0.36.1

Author: romancardenas

e310x/CHANGELOG.md

@@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Regenerate code with `svd2rust` 0.36.1
+- Use `riscv` v0.13.0 and `riscv-rt` v0.14.0
+- In vectored mode, align `mtvec` to 64 bytes
+
 ## [v0.12.0] - 2024-12-10
 
 ### Changed

e310x/Cargo.toml

@@ -12,9 +12,9 @@ edition = "2021"
 
 [dependencies]
 critical-section = { version = "1.2.0", optional = true }
-riscv = "0.12.0"
+riscv = "0.13.0"
 riscv-peripheral = "0.2.0"
-riscv-rt = { version = "0.13.0", features = ["no-interrupts"], optional = true }
+riscv-rt = { version = "0.14.0", features = ["no-interrupts"], optional = true }
 vcell = "0.1.3"
 
 [features]

e310x/build.rs

@@ -12,6 +12,8 @@ fn main() {
             .unwrap();
         println!("cargo:rustc-link-search={}", out.display());
         println!("cargo:rerun-if-changed=device.x");
+        println!("cargo:rustc-env=RISCV_MTVEC_ALIGN={}", 64usize);
+        println!("cargo:rerun-if-env-changed=RISCV_MTVEC_ALIGN");
     }
     println!("cargo:rerun-if-changed=build.rs");
 }

e310x/settings.yaml

@@ -50,3 +50,5 @@ riscv_config:
     name: "PLIC"
     core_interrupt: "MachineExternal"
     hart_id: "H0"
+
+  mtvec_align: 64

e310x/src/aonclk.rs

@@ -11,8 +11,7 @@ impl RegisterBlock {
         &self.lfrosccfg
     }
 }
-#[doc = "lfrosccfg (rw) register accessor: AON Clock Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lfrosccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lfrosccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lfrosccfg`]
-module"]
+#[doc = "lfrosccfg (rw) register accessor: AON Clock Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lfrosccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lfrosccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lfrosccfg`] module"]
 #[doc(alias = "lfrosccfg")]
 pub type Lfrosccfg = crate::Reg<lfrosccfg::LfrosccfgSpec>;
 #[doc = "AON Clock Configuration Register"]

e310x/src/aonclk/lfrosccfg.rs

@@ -72,10 +72,6 @@ impl crate::Readable for LfrosccfgSpec {}
 #[doc = "`write(|w| ..)` method takes [`lfrosccfg::W`](W) writer structure"]
 impl crate::Writable for LfrosccfgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets lfrosccfg to value 0"]
-impl crate::Resettable for LfrosccfgSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for LfrosccfgSpec {}

e310x/src/backup.rs

@@ -17,8 +17,7 @@ impl RegisterBlock {
         self.backup.iter()
     }
 }
-#[doc = "backup (rw) register accessor: Backup Register\n\nYou can [`read`](crate::Reg::read) this register and get [`backup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backup`]
-module"]
+#[doc = "backup (rw) register accessor: Backup Register\n\nYou can [`read`](crate::Reg::read) this register and get [`backup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backup`] module"]
 #[doc(alias = "backup")]
 pub type Backup = crate::Reg<backup::BackupSpec>;
 #[doc = "Backup Register"]

e310x/src/backup/backup.rs

@@ -18,11 +18,6 @@ impl crate::Readable for BackupSpec {}
 #[doc = "`write(|w| ..)` method takes [`backup::W`](W) writer structure"]
 impl crate::Writable for BackupSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-}
-#[doc = "`reset()` method sets backup[%s]
-to value 0"]
-impl crate::Resettable for BackupSpec {
-    const RESET_VALUE: u32 = 0;
 }
+#[doc = "`reset()` method sets backup[%s] to value 0"]
+impl crate::Resettable for BackupSpec {}

e310x/src/generic.rs

@@ -1,9 +1,54 @@
 use core::marker;
 
+/// Generic peripheral accessor
+pub struct Periph<RB, const A: usize> {
+    _marker: marker::PhantomData<RB>,
+}
+
+unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
+
+impl<RB, const A: usize> Periph<RB, A> {
+    ///Pointer to the register block
+    pub const PTR: *const RB = A as *const _;
+
+    ///Return the pointer to the register block
+    #[inline(always)]
+    pub const fn ptr() -> *const RB {
+        Self::PTR
+    }
+
+    /// Steal an instance of this peripheral
+    ///
+    /// # Safety
+    ///
+    /// Ensure that the new instance of the peripheral cannot be used in a way
+    /// that may race with any existing instances, for example by only
+    /// accessing read-only or write-only registers, or by consuming the
+    /// original peripheral and using critical sections to coordinate
+    /// access between multiple new instances.
+    ///
+    /// Additionally, other software such as HALs may rely on only one
+    /// peripheral instance existing to ensure memory safety; ensure
+    /// no stolen instances are passed to such software.
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: marker::PhantomData,
+        }
+    }
+}
+
+impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
+    type Target = RB;
+
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+
 /// Raw register type (`u8`, `u16`, `u32`, ...)
 pub trait RawReg:
     Copy
-    + Default
     + From<bool>
     + core::ops::BitOr<Output = Self>
     + core::ops::BitAnd<Output = Self>
@@ -14,8 +59,10 @@ pub trait RawReg:
 {
     /// Mask for bits of width `WI`
     fn mask<const WI: u8>() -> Self;
-    /// Mask for bits of width 1
-    fn one() -> Self;
+    /// `0`
+    const ZERO: Self;
+    /// `1`
+    const ONE: Self;
 }
 
 macro_rules! raw_reg {
@@ -25,10 +72,8 @@ macro_rules! raw_reg {
             fn mask<const WI: u8>() -> Self {
                 $mask::<WI>()
             }
-            #[inline(always)]
-            fn one() -> Self {
-                1
-            }
+            const ZERO: Self = 0;
+            const ONE: Self = 1;
         }
         const fn $mask<const WI: u8>() -> $U {
             <$U>::MAX >> ($size - WI)
@@ -74,10 +119,10 @@ pub trait Writable: RegisterSpec {
     type Safety;
 
     /// Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
 
     /// Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`
-    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
 }
 
 /// Reset value of the register.
@@ -86,7 +131,7 @@ pub trait Writable: RegisterSpec {
 /// register by using the `reset` method.
 pub trait Resettable: RegisterSpec {
     /// Reset value of the register.
-    const RESET_VALUE: Self::Ux;
+    const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
 
     /// Reset value of the register.
     #[inline(always)]
@@ -341,7 +386,7 @@ pub struct RangeTo<const MAX: u64>;
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
 
-impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
@@ -493,8 +538,8 @@ macro_rules! bit_proxy {
             /// Writes bit to the field
             #[inline(always)]
             pub fn bit(self, value: bool) -> &'a mut W<REG> {
-                self.w.bits &= !(REG::Ux::one() << self.o);
-                self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
+                self.w.bits &= !(REG::Ux::ONE << self.o);
+                self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
                 self.w
             }
             /// Writes `variant` to the field
@@ -522,13 +567,13 @@ where
     /// Sets the field bit
     #[inline(always)]
     pub fn set_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
     /// Clears the field bit
     #[inline(always)]
     pub fn clear_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -541,7 +586,7 @@ where
     /// Sets the field bit
     #[inline(always)]
     pub fn set_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
 }
@@ -554,7 +599,7 @@ where
     /// Clears the field bit
     #[inline(always)]
     pub fn clear_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -567,7 +612,7 @@ where
     ///Clears the field bit by passing one
     #[inline(always)]
     pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
 }
@@ -580,7 +625,7 @@ where
     ///Sets the field bit by passing zero
     #[inline(always)]
     pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -593,7 +638,7 @@ where
     ///Toggle the field bit by passing one
     #[inline(always)]
     pub fn toggle_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
 }
@@ -606,7 +651,7 @@ where
     ///Toggle the field bit by passing zero
     #[inline(always)]
     pub fn toggle_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -761,7 +806,7 @@ impl<REG: Writable> Reg<REG> {
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
         let value = f(&mut W {
-            bits: REG::Ux::default(),
+            bits: REG::Ux::ZERO,
             _reg: marker::PhantomData,
         })
         .bits;
@@ -782,7 +827,7 @@ impl<REG: Writable> Reg<REG> {
         F: FnOnce(&mut W<REG>) -> T,
     {
         let mut writer = W {
-            bits: REG::Ux::default(),
+            bits: REG::Ux::ZERO,
             _reg: marker::PhantomData,
         };