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fix transfer to wait for read bytes properly
1 parent 43a35ce commit 17aebc6

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src/spi/bus.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,8 @@ where
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// Ensure that RX FIFO is empty
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self.wait_for_rxfifo();
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134-
while iwrite < write.len() || iread < read.len() {
134+
// go through entire write buffer and read back (even if read buffer is empty)
135+
while iwrite < write.len() || iread < write.len() {
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if iwrite < write.len() && self.spi.txdata.read().full().bit_is_clear() {
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let byte = write.get(iwrite).unwrap_or(&0);
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iwrite += 1;

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