Questions about the priv signal in the interface between RISV hart and trace encoder

[Baixyzz]

From spec 4.2, we can see

priv[privilege_width_p-1:0] Privilege level for all instructions retired on this cycle.

But for interrupts and exceptions, they do not retire and may be accompanied by a change in privilege mode. So when ITYPE is equal to 1 or 2, should the accompanying PRIV signal output the privilege level where the trap occurs or the privilege level that handles the trap?

[Baixyzz]

@IainCRobertson About this question, can you give us some advices? Thanks.