Merge pull request #38 from kito-cheng/vec-constraint

kito-cheng · web-flow · commit e3110a0282a0 · 2023-04-28T20:20:36.000+08:00
Add inline asm operand constraints for vector register
diff --git a/riscv-c-api.md b/riscv-c-api.md
@@ -230,6 +230,9 @@ statements, including both RISC-V specific and common operand constraints.
 | I                  | 12-bit signed immediate integer operand      |      |
 | K                  | 5-bit unsigned immediate integer operand     |      |
 | J                  | Zero integer immediate operand                |      |
+| vr                 | Vector register                    |            |
+| vd                 | Vector register, excluding v0      |            |
+| vm                 | Vector register, only v0           |            |
 
 NOTE: Immediate value must be a compile-time constant.
 
