Skip to content

Commit d789053

Browse files
committed
Keep using some import * and variables in ctg and isca to support eval() working correctly
Signed-off-by: MingZhu Yan <yanmingzhu@iscas.ac.cn>
1 parent eeaeb03 commit d789053

File tree

3 files changed

+7
-2
lines changed

3 files changed

+7
-2
lines changed

riscv-ctg/riscv_ctg/constants.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22

33
import os
44
from math import sqrt
5+
from math import * # noqa: F403
56
from string import Template
67

78
root = os.path.abspath(os.path.dirname(__file__))

riscv-ctg/riscv_ctg/generator.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,11 @@
44
from constraint import Problem, MinConflictsSolver, AllDifferentConstraint
55
import re
66
from riscv_ctg.constants import twos, e_regset, signode_template, case_template, part_template, test_template, default_regset
7+
from riscv_ctg.constants import * # noqa: F403
78
from riscv_ctg.log import logger
89
from riscv_ctg.helpers import nan_box, sgn_extd, merge_fields_f, ExtractException
910
from riscv_ctg.dsp_function import gen_pair_reg_data, concat_simd_data
11+
from riscv_ctg.dsp_function import * # noqa: F403
1012
from riscv_isac.InstructionObject import instructionObject
1113
import struct
1214
import sys
@@ -1010,7 +1012,7 @@ def valreg(self,instr_dict):
10101012
else:
10111013
FLEN = 0
10121014
XLEN = max(self.opnode['xlen'])
1013-
_SIGALIGN = max(XLEN,FLEN)/8
1015+
SIGALIGN = max(XLEN,FLEN)/8 # noqa: F841
10141016
stride_sz = eval(suffix)
10151017
template = Template(eval(self.opnode['val']['val_template']))
10161018
width = self.iflen if self.is_fext else self.flen
@@ -1135,7 +1137,7 @@ def swreg(self, instr_dict):
11351137
else:
11361138
FLEN = 0
11371139
XLEN = max(self.opnode['xlen'])
1138-
_SIGALIGN = max(XLEN,FLEN)/8
1140+
SIGALIGN = max(XLEN,FLEN)/8 # noqa: F841
11391141
stride_sz = eval(suffix)
11401142
for instr in instr_dict:
11411143
if 'rs1' in instr and instr['rs1'] in available_reg:

riscv-isac/riscv_isac/cgf_normalize.py

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,11 @@
11
# See LICENSE.incore for details
22
from math import ceil, sqrt
3+
from math import * # noqa: F403
34
import riscv_isac.utils as utils
45
import itertools
56
import random
67
from riscv_isac.fp_dataset import logger
8+
from riscv_isac.fp_dataset import * # noqa: F403
79

810

911
def twos(val,bits):

0 commit comments

Comments
 (0)