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Physical Memory Protection (32/64) Tests and Covergroups (#462)
* PMP32 and PMP64 Covergroups added * YAML basedHeaders/Macros file for the coverpoints added * Added PMP32 and PMP64 ACTs * Added Changelog entry * PMP Macros added in Header file, PMP tests updated to support byte and half word access, PMP Coverpoints updated to a new pattern * 64 bit PMP Tests and coverpoints updated * 32 bit PMP Coverpoints updated to more compact version * Changelog entry removed for the PMP Tests and Coverpoints * Update rv32_pmp.cgf Updated pmp_cfg_locked_write_unrelated coverpoint based on Allen comment Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai> * Update rv64_pmp.cgf Updated pmp_cfg_locked_write_unrelated coverpoint in rv64 to update a minor bug Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai> * Changed the CI to see the artifacts * Reverted the change in CI * Removed __pycache__ folders * removed riscof work folder * RISCOF work folder in rv64 removed --------- Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai> Co-authored-by: umershahidengr <umer.shahid@10xengineers.ai> Co-authored-by: James Shi <shiqinghao.sqh@alibaba-inc.com>
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‎coverage/header_file.yaml

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‎coverage/rv32_pmp.cgf

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‎coverage/rv64_pmp.cgf

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‎riscv-test-suite/rv32i_m/pmp32/PMP-CFG-reg.S

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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
4+
// -----------
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//
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// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers
7+
// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing
8+
//
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// This assembly file tests access of pmp registers in M, S, and U mode.
10+
// pmp csrs are accessable only in M-mode so it should trap in S, and U mode.
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//
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/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf)
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pmpcfg0 & 0x20 == 0 : 0 // CHECK IF pmpcfg0[5]==0 (Hard wired zero bit)
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pmpcfg0 & 0x40 == 0 : 0 // CHECK IF pmpcfg0[6]==0 (Hard wired zero bit)
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pmpcfg0 & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[7]==1 (Lock bit)
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(pmpcfg0 >> 8) & 0x20 == 0 : 0 // CHECK IF pmpcfg0[13]==0 (Hard wired zero bit)
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(pmpcfg0 >> 8) & 0x40 == 0 : 0 // CHECK IF pmpcfg0[14]==0 (Hard wired zero bit)
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(pmpcfg0 >> 8) & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[15]==1 (Lock bit)
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(pmpcfg0 >> 16) & 0x20 == 0 : 0 // CHECK IF pmpcfg0[21]==0 (Hard wired zero bit)
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(pmpcfg0 >> 16) & 0x40 == 0 : 0 // CHECK IF pmpcfg0[22]==0 (Hard wired zero bit)
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(pmpcfg0 >> 16) & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[23]==1 (Lock bit)
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(pmpcfg0 >> 24) & 0x20 == 0 : 0 // CHECK IF pmpcfg0[29]==0 (Hard wired zero bit)
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(pmpcfg0 >> 24) & 0x40 == 0 : 0 // CHECK IF pmpcfg0[30]==0 (Hard wired zero bit)
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(pmpcfg0 >> 24) & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[31]==1 (Lock bit)
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// Same coverpoints are defined for pmpcfg1, pmpcfg2, and pmpcfg3
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// Details are given in /coverage/rv32i_priv.cgf
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*/
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32I_Zicsr")
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# Test code region
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMP_MACROS; mac PMP_helper_Coverpoints",pmp_cfg_locked_write_unrelated)
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RVTEST_SIGBASE( x3,signature_x3_1)
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.attribute unaligned_access, 0
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.attribute stack_align, 16
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.align 2
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.option norvc
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#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP)
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#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP)
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main:
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//////////////////////// INITIAL VALUES ////////////////////////////////
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LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test)
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LI(x9,0) // The register to carry offset value
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LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable
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// Loop to SET ALL pmpcfg REGs to zero
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.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
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.rept 4 // START OF LOOP
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csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value)
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.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
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.endr // END OF LOOP BODY
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// Loop to SET ALL pmpaddr REGs to zero
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.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
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.rept 16 // START OF LOOP
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csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value)
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.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
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.endr // END OF LOOP BODY
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//////////////////// Locked bit TEST 1 /////////////////////////////////////////////
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.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
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.rept 4 // START OF LOOP
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csrw pmpcfgi, a5 // WRITE pmpcfgi with ALL 1s, Locked the lock-bit [7,15,23,31]
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nop // Added nop in case of trap
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csrr a4, pmpcfgi // READ pmpcfgi
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// THIS READ WILL ALSO CONFIRM THE ZERO BITs OF PMPCFGi REG.
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// BIT 5-6, BIT 13-14, BIT 21-22, BIT 29-30 must be hardwired to zero
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// Verify that LOCKED bits are HIGH, and ZERO bits are zero
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RVTEST_SIGUPD(x3,a4)
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// TRY TO WRITE CFG REGISTER AGAIN (TRAP in case of LOCKED bit is HIGH)
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csrw pmpcfgi, x5 // WRITE pmpcfgi with some other values
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nop // Added nop in case of trap
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csrr a4, pmpcfgi // READ pmpcfgi
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// Since Locked bit is high, so this should return the old value!!!
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RVTEST_SIGUPD(x3,a4)
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.set pmpaddri, PMPADDR0+4*(pmpcfgi-PMPCFG0)
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// Initialize an iterating variable with the address of pmpaddr0 in 1st iteration (when pmpcfgi=pmpcfg0)
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// Initialize an iterating variable with the address of pmpaddr4 in 2nd iteration (when pmpcfgi=pmpcfg1)
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// Initialize an iterating variable with the address of pmpaddr8 in 3rd iteration (when pmpcfgi=pmpcfg2)
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// Initialize an iterating variable with the address of pmpaddr12 in 4th iteration (when pmpcfgi=pmpcfg3)
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.rept 4 // START OF LOOP
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// TRY TO WRITE ADDRESS REGISTER.
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csrw pmpaddri, a5 // WRITE pmpaddri with some other values
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// The updated write will give a trap!!!
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nop // Added nop in case of trap
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csrr a4, pmpaddri // READ pmpaddr0, value should not have been changed
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nop // Added nop in case of trap
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RVTEST_SIGUPD(x3,a4)
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.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
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.endr // END OF INNER LOOP BODY
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.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
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.endr // END OF OUTER LOOP BODY
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#endif
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# ---------------------------------------------------------------------------------------------
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# HALT
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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.word 0xbabecafe
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.word 0xbabecafe
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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rvtest_sig_begin:
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sig_begin_canary:
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CANARY;
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signature_x3_1:
123+
.fill 32*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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127+
tsig_begin_canary:
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CANARY;
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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tsig_end_canary:
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CANARY;
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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sig_end_canary:
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CANARY;
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rvtest_sig_end:
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RVMODEL_DATA_END

‎riscv-test-suite/rv32i_m/pmp32/PMP-CSR-access.S

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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
6+
// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers
7+
// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing
8+
//
9+
// This assembly file tests access of pmp registers in M, S, and U mode.
10+
// pmp csrs are accessable only in M-mode so it should trap in S, and U mode.
11+
//
12+
/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf)
13+
14+
// Details are given in /coverage/rv32i_priv.cgf
15+
*/
16+
//
17+
#define rvtest_strap_routine
18+
#include "model_test.h"
19+
#include "arch_test.h"
20+
RVTEST_ISA("RV32I_Zicsr")
21+
# Test code region
22+
.section .text.init
23+
.globl rvtest_entry_point
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rvtest_entry_point:
25+
RVMODEL_BOOT
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RVTEST_CODE_BEGIN
27+
#ifdef TEST_CASE_1
28+
RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",PMP_access_permission)
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RVTEST_SIGBASE( x13,signature_x13_1)
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.option nopic
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.attribute unaligned_access, 0
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.attribute stack_align, 16
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.align 2
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main:
35+
#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP)
36+
#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP)
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main:
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//////////////////////// INITIAL VALUES ////////////////////////////////
39+
LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test)
40+
LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable
41+
// Loop to SET ALL pmpcfg REGs to zero
42+
.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
43+
.rept 4 // START OF LOOP
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csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value)
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.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
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.endr // END OF LOOP BODY
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// Loop to SET ALL pmpaddr REGs to zero
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// Loop to SET ALL pmpaddr REGs to zero
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.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
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.rept 16 // START OF LOOP
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csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value)
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.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
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.endr // END OF LOOP BODY
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.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
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.rept 16 // START OF LOOP
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csrs pmpaddri, a5 // Set all pmpaddr regs to zero (initial value)
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.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
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.endr // END OF LOOP BODY
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//////////////// VERIFICATION /////////////////////////////////////////
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// READING pmpaddr in M-mode /////////////////////////////////////////
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.set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0
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.rept 16 // START OF LOOP
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csrr a4, pmpaddri // READING pmpaddri (i is from 0-15)
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nop // Added nop in case of trap
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RVTEST_SIGUPD(x13,a4) // Storing into signature file
66+
.set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg
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.endr // END OF LOOP BODY
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// WRITING pmpcfg registers //////////////////////////////////////////
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// Write in M-mode will be valid, Write in other modes will cause trap
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LI(a5, PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS NOT SET
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// Loop to Write ALL pmpcfg regs
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.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
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.rept 4 // START OF LOOP
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csrw pmpcfgi, a5 // Write pmpcfgi
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nop // Added nop in case of trap
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.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
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.endr // END OF LOOP BODY
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//////////////// VERIFICATION /////////////////////////////////////////
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// READING pmpcfg in M-mode /////////////////////////////////////////
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// Loop to verify the contents of pmpcfg regs
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.set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0
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.rept 4 // START OF LOOP
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csrr a4, pmpcfg0 // Read pmpcfg0
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nop // Added nop in case of trap
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RVTEST_SIGUPD(x13,a4)
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.set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg
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.endr // END OF LOOP BODY
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/////////////////// Switch to S-mode ////////////////////////////////////////////
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csrw satp, zero // Disable address translation.
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LI(t2, -1)
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csrw pmpaddr0, t2 // Updated pmpaddr0 to define PMP region consisting
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// of whole physical memory
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csrr t0, pmpaddr0 // Verify its value by reading back
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nop // Added nop in case of trap
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RVTEST_SIGUPD(x13,t0)
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nop // Added nop in case of trap
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LI(a5, PMP_L| PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS SET
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csrw pmpcfg0, a5
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RVTEST_GOTO_LOWER_MODE Smode // GO into S mode
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// REPEATING THE SAME TEST //////////////////////////////////////////
102+
// IN Smode now
103+
/////////////////// TEST 01 ////////////////////////////////////////////
104+
// WRITING pmpaddr registers //////////////////////////////////////////
105+
// Write in M-mode will be valid, Write in other modes will cause trap
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csrw pmpaddr0, x2 // Write pmpaddr0 in S mode (TRAP)
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nop // Added nop in case of trap
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// READING pmpaddr in S-mode /////////////////////////////////////////
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csrr a4, pmpaddr0 // Reading pmpaddr0 in S mode (TRAP)
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nop // Added nop in case of trap
111+
/////////////////// Switch back to M-mode ////////////////////////////////////////////
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RVTEST_GOTO_MMODE
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csrr a4, mstatus // VERIFICATION of M-mode
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nop // Added nop in case of trap
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RVTEST_SIGUPD(x13,a4)
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/////////////////// Switch to U-mode ////////////////////////////////////////////
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csrw satp, zero // Disable address translation.
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LI(t2, -1)
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csrw pmpaddr0, t2 // Updated pmpaddr0 to define PMP region consisting
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// of whole physical memory
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csrr t0, pmpaddr0 // Verify its value by reading back
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nop // Added nop in case of trap
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RVTEST_SIGUPD(x13,t0)
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nop // Added nop in case of trap
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LI(a5, PMP_L| PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS SET
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csrw pmpcfg0, a5
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// These steps are repeated and can be removed but it will make sure that you will switch mode
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// with full access on physical memory
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RVTEST_GOTO_LOWER_MODE Umode
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// REPEATING THE SAME TEST //////////////////////////////////////////
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// IN U-mode now
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/////////////////// TEST 01 ////////////////////////////////////////////
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// WRITING pmpaddr registers //////////////////////////////////////////
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// Write in M-mode will be valid, Write in other modes will cause trap
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csrw pmpaddr0, x2 // Write pmpaddr0 in u mode (TRAP)
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nop // Added nop in case of trap
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//////////////// VERIFICATION /////////////////////////////////////////
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// READING pmpaddr in S-mode /////////////////////////////////////////
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csrr a4, pmpaddr0 // Reading pmpaddr0 in U mode (TRAP)
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nop // Added nop in case of trap
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#endif
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# ---------------------------------------------------------------------------------------------
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# HALT
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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152+
rvtest_data:
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.word 0xbabecafe
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.word 0xbabecafe
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.word 0xbabecafe
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.word 0xbabecafe
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RVTEST_DATA_END
158+
159+
160+
RVMODEL_DATA_BEGIN
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rvtest_sig_begin:
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sig_begin_canary:
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CANARY;
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signature_x13_1:
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.fill 32*(XLEN/32),4,0xdeadbeef
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167+
#ifdef rvtest_mtrap_routine
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tsig_begin_canary:
170+
CANARY;
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mtrap_sigptr:
172+
.fill 64*(XLEN/32),4,0xdeadbeef
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tsig_end_canary:
174+
CANARY;
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176+
#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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183+
#endif
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sig_end_canary:
186+
CANARY;
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rvtest_sig_end:
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RVMODEL_DATA_END

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