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Add Zicbom and Zicbop extension
1 parent 88f90f5 commit 1b7ce27

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9 files changed

+219
-45
lines changed

9 files changed

+219
-45
lines changed

‎coverage/cmo/cbom.cgf

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
2+
3+
cbo.clean:
4+
config:
5+
- check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
6+
mnemonics:
7+
cbo.clean: 0
8+
rs1:
9+
<<: *all_regs_mx0
10+
val_comb:
11+
<<: [*base_rs1val_unsgn]
12+
abstract_comb:
13+
<<: [*rs1val_walking_unsgn]
14+
15+
cbo.flush:
16+
config:
17+
- check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
18+
mnemonics:
19+
cbo.flush: 0
20+
rs1:
21+
<<: *all_regs_mx0
22+
val_comb:
23+
<<: [*base_rs1val_unsgn]
24+
abstract_comb:
25+
<<: [*rs1val_walking_unsgn]
26+
27+
cbo.inval:
28+
config:
29+
- check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
30+
mnemonics:
31+
cbo.inval: 0
32+
rs1:
33+
<<: *all_regs_mx0
34+
val_comb:
35+
<<: [*base_rs1val_unsgn]
36+
abstract_comb:
37+
<<: [*rs1val_walking_unsgn]

‎coverage/cmo/cbop.cgf

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
2+
3+
prefetch.i:
4+
config:
5+
- check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
6+
mnemonics:
7+
prefetch.i: 0
8+
rs1:
9+
<<: *all_regs
10+
val_comb:
11+
<<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
12+
abstract_comb:
13+
<<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]
14+
15+
prefetch.r:
16+
config:
17+
- check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
18+
mnemonics:
19+
prefetch.r: 0
20+
rs1:
21+
<<: *all_regs
22+
val_comb:
23+
<<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
24+
abstract_comb:
25+
<<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]
26+
27+
prefetch.w:
28+
config:
29+
- check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
30+
mnemonics:
31+
prefetch.w: 0
32+
rs1:
33+
<<: *all_regs
34+
val_comb:
35+
<<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
36+
abstract_comb:
37+
<<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]

‎coverage/rv32i_cbo.cgf renamed to ‎coverage/cmo/cboz.cgf

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
22

3-
cbozero:
3+
cbo.zero:
44
config:
55
- check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
66
mnemonics:

‎coverage/cmo/rvi_cmo.cgf

Lines changed: 0 additions & 14 deletions
This file was deleted.

‎coverage/dataset.cgf

Lines changed: 25 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ datasets:
180180
x13: 0
181181
x14: 0
182182
x15: 0
183-
183+
184184
all_regs_mx2: &all_regs_mx2
185185
x1: 0
186186
x3: 0
@@ -295,7 +295,7 @@ datasets:
295295
r0fmt_op_comb: &r0fmt_op_comb
296296
'rs1 == 0': 0
297297
'rs1 != 0': 0
298-
298+
299299
base_rs1val_sgn: &base_rs1val_sgn
300300
'rs1_val == (-2**(xlen-1))': 0
301301
'rs1_val == 0': 0
@@ -307,7 +307,7 @@ datasets:
307307
'rs1_val == 0 and rs2_val == 0': 0
308308
'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0
309309
'rs1_val == 1 and rs2_val == 0': 0
310-
310+
311311
base_rs2val_sgn: &base_rs2val_sgn
312312
'rs2_val == (-2**(xlen-1))': 0
313313
'rs2_val == 0': 0
@@ -320,12 +320,11 @@ datasets:
320320
'rs3_val == (2**(xlen-1)-1)': 0
321321
'rs3_val == 1': 0
322322

323-
324323
base_rs1val_unsgn: &base_rs1val_unsgn
325324
'rs1_val == 0': 0
326325
'rs1_val == (2**(xlen)-1)': 0
327326
'rs1_val == 1': 0
328-
327+
329328
base_rs2val_unsgn: &base_rs2val_unsgn
330329
'rs2_val == 0': 0
331330
'rs2_val == (2**(xlen)-1)': 0
@@ -346,7 +345,7 @@ datasets:
346345

347346
div_corner_case: &div_corner_case
348347
'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0
349-
348+
350349
rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn
351350
'rs1_val > 0 and rs2_val > 0': 0
352351
'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0
@@ -364,12 +363,23 @@ datasets:
364363
'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0
365364
'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0
366365

366+
zicbop_ifmt_val_comb_unsgn: &zicbop_ifmt_val_comb_unsgn
367+
'rs1_val == imm_val and rs1_val == 0': 0
368+
'rs1_val < imm_val and rs1_val != 0': 0
369+
'rs1_val > imm_val and imm_val == 0': 0
370+
367371
ifmt_base_immval_sgn: &ifmt_base_immval_sgn
368372
'imm_val == (-2**(12-1))': 0
369373
'imm_val == 0': 0
370374
'imm_val == (2**(12-1)-1)': 0
371375
'imm_val == 1': 0
372376

377+
ifmt_base_immval11_5_sgn: &ifmt_base_immval11_5_sgn
378+
'imm_val == (-2**(7-1)) << 5': 0
379+
'imm_val == 0': 0
380+
'imm_val == (2**(7-1)-1) << 5': 0
381+
'imm_val == 1<<5': 0
382+
373383
ifmt_base_immval_sgn_len: &ifmt_base_immval_sgn_len
374384
'imm_val == (-2**(ceil(log(xlen,2))-1))': 0
375385
'imm_val == 0': 0
@@ -435,7 +445,7 @@ datasets:
435445
'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
436446
'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0
437447
'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
438-
448+
439449
bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn
440450
'rs1_val > 0 and rs2_val > 0': 0
441451
'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0
@@ -480,12 +490,17 @@ datasets:
480490
'walking_ones("imm_val", 5, False)': 0
481491
'walking_zeros("imm_val", 5, False)': 0
482492
'alternate("imm_val", 5, False)': 0
483-
493+
494+
ifmt_immval_walking_11_5: &ifmt_immval_walking_11_5
495+
'walking_ones("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
496+
'walking_zeros("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
497+
'alternate("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
498+
484499
rs1val_walking_unsgn: &rs1val_walking_unsgn
485500
'walking_ones("rs1_val", xlen,False)': 0
486501
'walking_zeros("rs1_val", xlen,False)': 0
487502
'alternate("rs1_val",xlen,False)': 0
488-
503+
489504
rs2val_walking_unsgn: &rs2val_walking_unsgn
490505
'walking_ones("rs2_val", xlen,False)': 0
491506
'walking_zeros("rs2_val", xlen,False)': 0
@@ -499,7 +514,7 @@ datasets:
499514
'walking_ones("imm_val", 6)': 0
500515
'walking_zeros("imm_val", 6)': 0
501516
'alternate("imm_val",6)': 0
502-
517+
503518
ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn
504519
'walking_ones("imm_val", 12,False)': 0
505520
'walking_zeros("imm_val", 12,False)': 0

‎coverage/rv64i_cbo.cgf

Lines changed: 0 additions & 14 deletions
This file was deleted.

‎riscv-ctg/riscv_ctg/data/template.yaml

Lines changed: 108 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10423,15 +10423,120 @@ cbo.zero:
1042310423
sz: 'RVMODEL_CBZ_BLOCKSIZE'
1042410424
xlen: [32,64]
1042510425
isa:
10426-
- IZicbozZicsr
10426+
- IZicboz_Zicsr
1042710427
formattype: 'zformat'
1042810428
rs1_op_data: *all_regs_mx0
10429-
rs1_val_data: 'gen_usign_dataset(12)'
10429+
rs1_val_data: 'gen_usign_dataset(12) + gen_sp_dataset(xlen,False)'
1043010430
template: |-
1043110431
1043210432
// $comment
1043310433
// opcode: $inst ; op1:$rs1; op1val:$rs1_val
10434-
TEST_CBO_ZERO($swreg,$rs1,$inst,$rs1_val)
10434+
TEST_CBO($swreg,$rs1,$inst,$rs1_val)
10435+
10436+
cbo.clean:
10437+
std_op:
10438+
sig:
10439+
stride: 1
10440+
sz: 'XLEN/8'
10441+
xlen: [32,64]
10442+
isa:
10443+
- IZicbom_Zicsr
10444+
formattype: 'zformat'
10445+
rs1_op_data: *all_regs
10446+
rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
10447+
template: |-
10448+
10449+
// $comment
10450+
// opcode: $inst ; op1:$rs1; op1val:$rs1_val
10451+
TEST_CBO($swreg,$rs1,$inst,$rs1_val)
10452+
10453+
cbo.flush:
10454+
std_op:
10455+
sig:
10456+
stride: 1
10457+
sz: 'XLEN/8'
10458+
xlen: [32,64]
10459+
isa:
10460+
- IZicbom_Zicsr
10461+
formattype: 'zformat'
10462+
rs1_op_data: *all_regs
10463+
rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
10464+
template: |-
10465+
10466+
// $comment
10467+
// opcode: $inst ; op1:$rs1; op1val:$rs1_val
10468+
TEST_CBO($swreg,$rs1,$inst,$rs1_val)
10469+
10470+
cbo.inval:
10471+
std_op:
10472+
sig:
10473+
stride: 1
10474+
sz: 'XLEN/8'
10475+
xlen: [32,64]
10476+
isa:
10477+
- IZicbom_Zicsr
10478+
formattype: 'zformat'
10479+
rs1_op_data: *all_regs
10480+
rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
10481+
template: |-
10482+
10483+
// $comment
10484+
// opcode: $inst ; op1:$rs1; op1val:$rs1_val
10485+
TEST_CBO($swreg,$rs1,$inst,$rs1_val)
10486+
10487+
prefetch.i:
10488+
sig:
10489+
stride: 1
10490+
sz: 'XLEN/8'
10491+
xlen: [32,64]
10492+
std_op:
10493+
isa:
10494+
- IZicbop_Zicsr
10495+
formattype: 'iformat'
10496+
rs1_op_data: *all_regs
10497+
rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
10498+
imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
10499+
template: |-
10500+
10501+
// $comment
10502+
// opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
10503+
TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
10504+
10505+
prefetch.r:
10506+
sig:
10507+
stride: 1
10508+
sz: 'XLEN/8'
10509+
xlen: [32,64]
10510+
std_op:
10511+
isa:
10512+
- IZicbop_Zicsr
10513+
formattype: 'iformat'
10514+
rs1_op_data: *all_regs
10515+
rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)'
10516+
imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
10517+
template: |-
10518+
10519+
// $comment
10520+
// opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
10521+
TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
10522+
10523+
prefetch.w:
10524+
sig:
10525+
stride: 1
10526+
sz: 'XLEN/8'
10527+
xlen: [32,64]
10528+
std_op:
10529+
isa:
10530+
- IZicbop_Zicsr
10531+
formattype: 'iformat'
10532+
rs1_op_data: *all_regs
10533+
rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)'
10534+
imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
10535+
template: |-
10536+
10537+
// $comment
10538+
// opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
10539+
TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
1043510540
1043610541
amoadd.w:
1043710542
sig:

‎riscv-ctg/riscv_ctg/generator.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ def get_rm(opcode):
172172
'prrformat': '["rs1_val", "rs2_val"]',
173173
'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']",
174174
'dcasrformat': '["rs1_val", "rs2_val"]',
175-
'zformat': ['rs1']
175+
'zformat': "['rs1_val']"
176176
}
177177
''' Dictionary mapping instruction formats to operand value variables used by those formats '''
178178

@@ -1138,6 +1138,7 @@ def swreg(self, instr_dict):
11381138
else:
11391139
FLEN = 0
11401140
XLEN = max(self.opnode['xlen'])
1141+
RVMODEL_CBZ_BLOCKSIZE = XLEN
11411142
SIGALIGN = max(XLEN,FLEN)/8
11421143
stride_sz = eval(suffix)
11431144
for instr in instr_dict:

‎riscv-test-suite/env/test_macros.h

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -769,14 +769,21 @@ nop ;\
769769
csrr flagreg, fcsr ;\
770770
RVTEST_SIGUPD_F(swreg,destreg,flagreg)
771771

772-
#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val) ;\
773-
LI(rs1,imm_val&(RVMODEL_CBZ_BLOCKSIZE-1)) ;\
772+
#define TEST_CBO(swreg,rs1,inst,rs1_val) ;\
773+
LI(rs1,rs1_val&(RVMODEL_CBZ_BLOCKSIZE-1)) ;\
774774
add rs1,rs1,swreg ;\
775775
inst (rs1) ;\
776776
nop ;\
777777
nop ;\
778778
ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
779779

780+
#define TEST_PREFETCH(swreg,rs1,inst,rs1_val,imm_val) ;\
781+
LI(rs1,rs1_val) ;\
782+
inst imm_val(rs1) ;\
783+
nop ;\
784+
nop ;\
785+
ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
786+
780787
#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) ;\
781788
LI(TEMP_REG,VAL) ;\
782789
and TEMP_REG,TEMP_REG,MASK_REG ;\

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