From f780c27af43712c16f961a9fcf04c0241685f47a Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Tue, 29 Apr 2025 18:59:15 +0300 Subject: [PATCH 1/3] Update image in `build32` Ubuntu 20.04 is no longer available. See https://github.com/actions/runner-images/issues/11101 Checkpatch-ignore: BAD_SIGN_OFF Change-Id: I0ec3e3342f9212a2a79d8dca6274e7db62ecedab Signed-off-by: Evgeniy Naydanov --- .github/workflows/linux-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linux-build.yml b/.github/workflows/linux-build.yml index 4bcd5bb809..c21b36465c 100644 --- a/.github/workflows/linux-build.yml +++ b/.github/workflows/linux-build.yml @@ -5,7 +5,7 @@ name: Linux Build jobs: # 32-bit, clang build32: - runs-on: ubuntu-20.04 + runs-on: ubuntu-latest env: CFLAGS: -m32 CC: clang From 64ea3296f33c57bc21ac0113c9049f8988d5a0d0 Mon Sep 17 00:00:00 2001 From: "zhefan.lv" Date: Thu, 15 May 2025 16:32:19 +0800 Subject: [PATCH 2/3] target/riscv: VU mode address translation not care hstatus.HU When vmode=1 and effective_mode=PRV_U, it is VU mode but not U mode, address translation don't need to care hstatus.HU. Whether MMU is enabled depends on hgatp mode and vsatp mode. --- src/target/riscv/riscv.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index aae5eb35a9..393da3e227 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -3035,23 +3035,6 @@ static int riscv_mmu(struct target *target, int *enabled) unsigned int xlen = riscv_xlen(target); if (v_mode) { - /* vsatp and hgatp registers are considered active for the - * purposes of the address-translation algorithm unless the - * effective privilege mode is U and hstatus.HU=0. */ - if (effective_mode == PRV_U) { - riscv_reg_t hstatus; - if (riscv_reg_get(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) { - LOG_TARGET_ERROR(target, "Failed to read hstatus register."); - return ERROR_FAIL; - } - - if (get_field(hstatus, HSTATUS_HU) == 0) - /* In hypervisor mode regular satp translation - * doesn't happen. */ - return ERROR_OK; - - } - riscv_reg_t vsatp; if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64, From b72b83a59b944586f99a6bf604446aa950776fde Mon Sep 17 00:00:00 2001 From: Mark Zhuang Date: Fri, 16 May 2025 11:06:10 +0800 Subject: [PATCH 3/3] target/riscv: fix get mode filed for vsatp and hgatp Add the necessary get_filed and add a comment to indicate this section is for VU/VS mode --- src/target/riscv/riscv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 393da3e227..2e475a5d4f 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -3035,6 +3035,8 @@ static int riscv_mmu(struct target *target, int *enabled) unsigned int xlen = riscv_xlen(target); if (v_mode) { + /* In VU or VS mode, MMU is considered enabled when + * either hgatp or vsatp mode is not OFF */ riscv_reg_t vsatp; if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) { LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64, @@ -3042,7 +3044,7 @@ static int riscv_mmu(struct target *target, int *enabled) return ERROR_FAIL; } /* vsatp is identical to satp, so we can use the satp macros. */ - if (RISCV_SATP_MODE(xlen) != SATP_MODE_OFF) { + if (get_field(vsatp, RISCV_SATP_MODE(xlen)) != SATP_MODE_OFF) { LOG_TARGET_DEBUG(target, "VS-stage translation is enabled."); *enabled = 1; return ERROR_OK; @@ -3054,7 +3056,7 @@ static int riscv_mmu(struct target *target, int *enabled) priv); return ERROR_FAIL; } - if (RISCV_HGATP_MODE(xlen) != HGATP_MODE_OFF) { + if (get_field(hgatp, RISCV_HGATP_MODE(xlen)) != HGATP_MODE_OFF) { LOG_TARGET_DEBUG(target, "G-stage address translation is enabled."); *enabled = 1; } else {