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target/riscv: fix get mode filed for vsatp and hgatp
Add the necessary get_filed and add a comment to indicate this section is for VU/VS mode
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src/target/riscv/riscv.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3035,14 +3035,16 @@ static int riscv_mmu(struct target *target, int *enabled)
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unsigned int xlen = riscv_xlen(target);
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if (v_mode) {
3038+
/* In VU or VS mode, MMU is considered enabled when
3039+
* either hgatp or vsatp mode is not OFF */
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riscv_reg_t vsatp;
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if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,
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priv);
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return ERROR_FAIL;
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}
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/* vsatp is identical to satp, so we can use the satp macros. */
3045-
if (RISCV_SATP_MODE(xlen) != SATP_MODE_OFF) {
3047+
if (get_field(vsatp, RISCV_SATP_MODE(xlen)) != SATP_MODE_OFF) {
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LOG_TARGET_DEBUG(target, "VS-stage translation is enabled.");
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*enabled = 1;
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return ERROR_OK;
@@ -3054,7 +3056,7 @@ static int riscv_mmu(struct target *target, int *enabled)
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priv);
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return ERROR_FAIL;
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}
3057-
if (RISCV_HGATP_MODE(xlen) != HGATP_MODE_OFF) {
3059+
if (get_field(hgatp, RISCV_HGATP_MODE(xlen)) != HGATP_MODE_OFF) {
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LOG_TARGET_DEBUG(target, "G-stage address translation is enabled.");
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*enabled = 1;
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} else {

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