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Revert "drm/v3d: Use V3D_SMS registers for power on/off and reset on V3D 7.x"
This reverts commit 850bf1a.
1 parent 35ed272 commit f37b8c3

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4 files changed

+0
-56
lines changed

4 files changed

+0
-56
lines changed

drivers/gpu/drm/v3d/v3d_drv.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -482,8 +482,6 @@ static void v3d_platform_drm_remove(struct platform_device *pdev)
482482
dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
483483
v3d->mmu_scratch_paddr);
484484

485-
v3d_power_off_sms(v3d);
486-
487485
clk_disable_unprepare(v3d->clk);
488486
}
489487

drivers/gpu/drm/v3d/v3d_drv.h

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,6 @@ struct v3d_dev {
118118
void __iomem *core_regs[3];
119119
void __iomem *bridge_regs;
120120
void __iomem *gca_regs;
121-
void __iomem *sms_regs;
122121
struct clk *clk;
123122
struct delayed_work clk_down_work;
124123
unsigned long clk_up_rate, clk_down_rate;
@@ -275,15 +274,6 @@ to_v3d_fence(struct dma_fence *fence)
275274
#define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
276275
#define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
277276

278-
#define V3D_SMS_IDLE 0x0
279-
#define V3D_SMS_ISOLATING_FOR_RESET 0xa
280-
#define V3D_SMS_RESETTING 0xb
281-
#define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc
282-
#define V3D_SMS_POWER_OFF_STATE 0xd
283-
284-
#define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset))
285-
#define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset))
286-
287277
#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
288278
#define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
289279

@@ -562,7 +552,6 @@ struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
562552
/* v3d_gem.c */
563553
int v3d_gem_init(struct drm_device *dev);
564554
void v3d_gem_destroy(struct drm_device *dev);
565-
void v3d_reset_sms(struct v3d_dev *v3d);
566555
void v3d_reset(struct v3d_dev *v3d);
567556
void v3d_invalidate_caches(struct v3d_dev *v3d);
568557
void v3d_clean_caches(struct v3d_dev *v3d);

drivers/gpu/drm/v3d/v3d_gem.c

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -105,22 +105,6 @@ v3d_reset_v3d(struct v3d_dev *v3d)
105105
v3d_init_hw_state(v3d);
106106
}
107107

108-
void
109-
v3d_reset_sms(struct v3d_dev *v3d)
110-
{
111-
if (v3d->ver < V3D_GEN_71)
112-
return;
113-
114-
V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE));
115-
116-
if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
117-
V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) &&
118-
!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
119-
V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) {
120-
DRM_ERROR("Failed to wait for SMS reset\n");
121-
}
122-
}
123-
124108
void
125109
v3d_reset(struct v3d_dev *v3d)
126110
{
@@ -136,7 +120,6 @@ v3d_reset(struct v3d_dev *v3d)
136120
v3d_idle_axi(v3d, 0);
137121

138122
v3d_idle_gca(v3d);
139-
v3d_reset_sms(v3d);
140123
v3d_reset_v3d(v3d);
141124

142125
v3d_mmu_set_page_table(v3d);

drivers/gpu/drm/v3d/v3d_regs.h

Lines changed: 0 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -515,30 +515,4 @@
515515
# define V3D_ERR_VPAERGS BIT(1)
516516
# define V3D_ERR_VPAEABB BIT(0)
517517

518-
#define V3D_SMS_REE_CS 0x00000
519-
#define V3D_SMS_TEE_CS 0x00400
520-
# define V3D_SMS_INTERRUPT BIT(31)
521-
# define V3D_SMS_POWER_OFF BIT(30)
522-
# define V3D_SMS_CLEAR_POWER_OFF BIT(29)
523-
# define V3D_SMS_LOCK BIT(28)
524-
# define V3D_SMS_CLEAR_LOCK BIT(27)
525-
# define V3D_SMS_SVP_MODE_EXIT BIT(26)
526-
# define V3D_SMS_CLEAR_SVP_MODE_EXIT BIT(25)
527-
# define V3D_SMS_SVP_MODE_ENTER BIT(24)
528-
# define V3D_SMS_CLEAR_SVP_MODE_ENTER BIT(23)
529-
# define V3D_SMS_THEIR_MODE_EXIT BIT(22)
530-
# define V3D_SMS_THEIR_MODE_ENTER BIT(21)
531-
# define V3D_SMS_OUR_MODE_EXIT BIT(20)
532-
# define V3D_SMS_CLEAR_OUR_MODE_EXIT BIT(19)
533-
# define V3D_SMS_SEQ_PC_MASK V3D_MASK(16, 10)
534-
# define V3D_SMS_SEQ_PC_SHIFT 10
535-
# define V3D_SMS_HUBCORE_STATUS_MASK V3D_MASK(9, 8)
536-
# define V3D_SMS_HUBCORE_STATUS_SHIFT 8
537-
# define V3D_SMS_NEW_MODE_MASK V3D_MASK(7, 6)
538-
# define V3D_SMS_NEW_MODE_SHIFT 6
539-
# define V3D_SMS_OLD_MODE_MASK V3D_MASK(5, 4)
540-
# define V3D_SMS_OLD_MODE_SHIFT 4
541-
# define V3D_SMS_STATE_MASK V3D_MASK(3, 0)
542-
# define V3D_SMS_STATE_SHIFT 0
543-
544518
#endif /* V3D_REGS_H */

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