Skip to content

Commit d978bac

Browse files
Stanimir Varbanovpopcornmix
authored andcommitted
dt-bindings: interrupt-controller: Add bcm2712 MSI-X DT bindings
Adds DT bindings for bcm2712 MSI-X interrupt peripheral controller. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
1 parent afdea51 commit d978bac

File tree

1 file changed

+60
-0
lines changed

1 file changed

+60
-0
lines changed
Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
8+
9+
maintainers:
10+
- Stanimir Varbanov <svarbanov@suse.de>
11+
12+
description:
13+
This interrupt controller is used to provide interrupt vectors to the
14+
generic interrupt controller (GIC) on bcm2712. It will be used as
15+
external MSI-X controller for PCIe root complex.
16+
17+
allOf:
18+
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
19+
20+
properties:
21+
compatible:
22+
const: brcm,bcm2712-mip
23+
24+
reg:
25+
items:
26+
- description: Base register address
27+
- description: PCIe message address
28+
29+
"#msi-cells":
30+
const: 0
31+
32+
brcm,msi-offset:
33+
$ref: /schemas/types.yaml#/definitions/uint32
34+
description: Shift the allocated MSI's.
35+
36+
unevaluatedProperties: false
37+
38+
required:
39+
- compatible
40+
- reg
41+
- msi-controller
42+
- msi-ranges
43+
44+
examples:
45+
- |
46+
#include <dt-bindings/interrupt-controller/arm-gic.h>
47+
48+
axi {
49+
#address-cells = <2>;
50+
#size-cells = <2>;
51+
52+
msi-controller@1000130000 {
53+
compatible = "brcm,bcm2712-mip";
54+
reg = <0x10 0x00130000 0x00 0xc0>,
55+
<0xff 0xfffff000 0x00 0x1000>;
56+
msi-controller;
57+
#msi-cells = <0>;
58+
msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
59+
};
60+
};

0 commit comments

Comments
 (0)