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overlay: Rework/fix the Pi 5 MIDI UART overlays
The old Pi 5 MIDI UART overlays replaced the reference to the UART's source clock with a fixed clock (essentially an integer dressed up like a clock). This is fragile, in that the fixed clock must be updated if the source clock's (fixed) frequency is ever changed, but it also relies on the source clock having been enabled, which is likely not to be the case unless another RP1 UART is being actively used. Switching to a fixed-factor-clock solves both of those problems. See: https://forums.raspberrypi.com/viewtopic.php?t=385906 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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5 files changed

+55
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arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,32 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 50MHz, which we scale so that requesting
9-
* 38.4kHz results in an actual 31.25kHz.
10-
*
11-
* 50000000*38400/31250 = 61440000
8+
* baudrate. Create an intermediary clock that reports the real clock frequency
9+
* multiplied by 38400/31250. This will result in the UART's clock divisor being
10+
* greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11+
* an actual 31.25kHz.
1212
*/
1313

1414
/{
1515
compatible = "brcm,bcm2712";
1616

1717
fragment@0 {
18-
target-path = "/";
18+
target-path = "/clocks";
1919
__overlay__ {
20-
midi_clk: midi_clk0 {
21-
compatible = "fixed-clock";
20+
midi_clk: midiclock_0 {
21+
compatible = "fixed-factor-clock";
2222
#clock-cells = <0>;
23-
clock-output-names = "uart0_pclk";
24-
clock-frequency = <61440000>;
23+
clocks = <&rp1_clocks RP1_CLK_UART>;
24+
clock-mult = <38400>;
25+
clock-div = <31250>;
2526
};
2627
};
2728
};
2829

2930
fragment@1 {
3031
target = <&uart0>;
3132
__overlay__ {
33+
status = "okay";
3234
clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
3335
};
3436
};

arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,32 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 50MHz, which we scale so that requesting
9-
* 38.4kHz results in an actual 31.25kHz.
10-
*
11-
* 50000000*38400/31250 = 61440000
8+
* baudrate. Create an intermediary clock that reports the real clock frequency
9+
* multiplied by 38400/31250. This will result in the UART's clock divisor being
10+
* greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11+
* an actual 31.25kHz.
1212
*/
1313

1414
/{
1515
compatible = "brcm,bcm2712";
1616

1717
fragment@0 {
18-
target-path = "/";
18+
target-path = "/clocks";
1919
__overlay__ {
20-
midi_clk: midi_clk1 {
21-
compatible = "fixed-clock";
20+
midi_clk: midiclock_1 {
21+
compatible = "fixed-factor-clock";
2222
#clock-cells = <0>;
23-
clock-output-names = "uart1_pclk";
24-
clock-frequency = <61440000>;
23+
clocks = <&rp1_clocks RP1_CLK_UART>;
24+
clock-mult = <38400>;
25+
clock-div = <31250>;
2526
};
2627
};
2728
};
2829

2930
fragment@1 {
3031
target = <&uart1>;
3132
__overlay__ {
33+
status = "okay";
3234
clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
3335
};
3436
};

arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,32 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 50MHz, which we scale so that requesting
9-
* 38.4kHz results in an actual 31.25kHz.
10-
*
11-
* 50000000*38400/31250 = 61440000
8+
* baudrate. Create an intermediary clock that reports the real clock frequency
9+
* multiplied by 38400/31250. This will result in the UART's clock divisor being
10+
* greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11+
* an actual 31.25kHz.
1212
*/
1313

1414
/{
1515
compatible = "brcm,bcm2712";
1616

1717
fragment@0 {
18-
target-path = "/";
18+
target-path = "/clocks";
1919
__overlay__ {
20-
midi_clk: midi_clk2 {
21-
compatible = "fixed-clock";
20+
midi_clk: midiclock_2 {
21+
compatible = "fixed-factor-clock";
2222
#clock-cells = <0>;
23-
clock-output-names = "uart2_pclk";
24-
clock-frequency = <61440000>;
23+
clocks = <&rp1_clocks RP1_CLK_UART>;
24+
clock-mult = <38400>;
25+
clock-div = <31250>;
2526
};
2627
};
2728
};
2829

2930
fragment@1 {
3031
target = <&uart2>;
3132
__overlay__ {
33+
status = "okay";
3234
clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
3335
};
3436
};

arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,32 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 50MHz, which we scale so that requesting
9-
* 38.4kHz results in an actual 31.25kHz.
10-
*
11-
* 50000000*38400/31250 = 61440000
8+
* baudrate. Create an intermediary clock that reports the real clock frequency
9+
* multiplied by 38400/31250. This will result in the UART's clock divisor being
10+
* greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11+
* an actual 31.25kHz.
1212
*/
1313

1414
/{
1515
compatible = "brcm,bcm2712";
1616

1717
fragment@0 {
18-
target-path = "/";
18+
target-path = "/clocks";
1919
__overlay__ {
20-
midi_clk: midi_clk3 {
21-
compatible = "fixed-clock";
20+
midi_clk: midiclock_3 {
21+
compatible = "fixed-factor-clock";
2222
#clock-cells = <0>;
23-
clock-output-names = "uart3_pclk";
24-
clock-frequency = <61440000>;
23+
clocks = <&rp1_clocks RP1_CLK_UART>;
24+
clock-mult = <38400>;
25+
clock-div = <31250>;
2526
};
2627
};
2728
};
2829

2930
fragment@1 {
3031
target = <&uart3>;
3132
__overlay__ {
33+
status = "okay";
3234
clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
3335
};
3436
};

arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,32 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 50MHz, which we scale so that requesting
9-
* 38.4kHz results in an actual 31.25kHz.
10-
*
11-
* 50000000*38400/31250 = 61440000
8+
* baudrate. Create an intermediary clock that reports the real clock frequency
9+
* multiplied by 38400/31250. This will result in the UART's clock divisor being
10+
* greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11+
* an actual 31.25kHz.
1212
*/
1313

1414
/{
1515
compatible = "brcm,bcm2712";
1616

1717
fragment@0 {
18-
target-path = "/";
18+
target-path = "/clocks";
1919
__overlay__ {
20-
midi_clk: midi_clk4 {
21-
compatible = "fixed-clock";
20+
midi_clk: midiclock_4 {
21+
compatible = "fixed-factor-clock";
2222
#clock-cells = <0>;
23-
clock-output-names = "uart4_pclk";
24-
clock-frequency = <61440000>;
23+
clocks = <&rp1_clocks RP1_CLK_UART>;
24+
clock-mult = <38400>;
25+
clock-div = <31250>;
2526
};
2627
};
2728
};
2829

2930
fragment@1 {
3031
target = <&uart4>;
3132
__overlay__ {
33+
status = "okay";
3234
clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
3335
};
3436
};

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