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arch/arm/boot/dts/overlays Expand file tree Collapse file tree 5 files changed +55
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lines changed Original file line number Diff line number Diff line change 5
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks ";
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__overlay__ {
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- midi_clk: midi_clk0 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_0 {
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+ compatible = "fixed-factor- clock";
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#clock-cells = <0>;
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- clock-output-names = "uart0_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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fragment@1 {
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target = <&uart0>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
Original file line number Diff line number Diff line change 5
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks ";
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__overlay__ {
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- midi_clk: midi_clk1 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_1 {
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+ compatible = "fixed-factor- clock";
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#clock-cells = <0>;
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- clock-output-names = "uart1_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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fragment@1 {
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target = <&uart1>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
Original file line number Diff line number Diff line change 5
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 50MHz, which we scale so that requesting
9
- * 38.4kHz results in an actual 31.25kHz.
10
- *
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- * 50000000*38400/31250 = 61440000
8
+ * baudrate. Create an intermediary clock that reports the real clock frequency
9
+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
10
+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks ";
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__overlay__ {
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- midi_clk: midi_clk2 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_2 {
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+ compatible = "fixed-factor- clock";
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#clock-cells = <0>;
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- clock-output-names = "uart2_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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fragment@1 {
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target = <&uart2>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
Original file line number Diff line number Diff line change 5
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/*
7
7
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 50MHz, which we scale so that requesting
9
- * 38.4kHz results in an actual 31.25kHz.
10
- *
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- * 50000000*38400/31250 = 61440000
8
+ * baudrate. Create an intermediary clock that reports the real clock frequency
9
+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
10
+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11
+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks ";
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__overlay__ {
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- midi_clk: midi_clk3 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_3 {
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+ compatible = "fixed-factor- clock";
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#clock-cells = <0>;
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- clock-output-names = "uart3_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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fragment@1 {
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target = <&uart3>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
Original file line number Diff line number Diff line change 5
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/*
7
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 50MHz, which we scale so that requesting
9
- * 38.4kHz results in an actual 31.25kHz.
10
- *
11
- * 50000000*38400/31250 = 61440000
8
+ * baudrate. Create an intermediary clock that reports the real clock frequency
9
+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
10
+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
11
+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks ";
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__overlay__ {
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- midi_clk: midi_clk4 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_4 {
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+ compatible = "fixed-factor- clock";
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#clock-cells = <0>;
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- clock-output-names = "uart4_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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fragment@1 {
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target = <&uart4>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
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