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PCI: brcmstb: Use same constant table for config space access
The constants EXT_CFG_DATA and EXT_CFG_INDEX vary by SOC. One of the map_bus methods used these constants, the other used different constants. Fortunately there was no problem because the SoCs that used the latter map_bus method all had the same register constants. Remove the redundant constants and adjust the code to use them. In addition, update EXT_CFG_DATA to use the 4k-page based config space access system, which is what the second map_bus method was already using. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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drivers/pci/controller/pcie-brcmstb.c

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -150,9 +150,6 @@
150150
#define MSI_INT_MASK_SET 0x10
151151
#define MSI_INT_MASK_CLR 0x14
152152

153-
#define PCIE_EXT_CFG_DATA 0x8000
154-
#define PCIE_EXT_CFG_INDEX 0x9000
155-
156153
#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
157154
#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
158155

@@ -727,8 +724,8 @@ static void __iomem *brcm_pcie_map_bus(struct pci_bus *bus,
727724

728725
/* For devices, write to the config space index register */
729726
idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
730-
writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
731-
return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
727+
writel(idx, base + IDX_ADDR(pcie));
728+
return base + DATA_ADDR(pcie) + PCIE_ECAM_REG(where);
732729
}
733730

734731
static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
@@ -1711,15 +1708,15 @@ static void brcm_pcie_remove(struct platform_device *pdev)
17111708
static const int pcie_offsets[] = {
17121709
[RGR1_SW_INIT_1] = 0x9210,
17131710
[EXT_CFG_INDEX] = 0x9000,
1714-
[EXT_CFG_DATA] = 0x9004,
1711+
[EXT_CFG_DATA] = 0x8000,
17151712
[PCIE_HARD_DEBUG] = 0x4204,
17161713
[PCIE_INTR2_CPU_BASE] = 0x4300,
17171714
};
17181715

17191716
static const int pcie_offsets_bcm7278[] = {
17201717
[RGR1_SW_INIT_1] = 0xc010,
17211718
[EXT_CFG_INDEX] = 0x9000,
1722-
[EXT_CFG_DATA] = 0x9004,
1719+
[EXT_CFG_DATA] = 0x8000,
17231720
[PCIE_HARD_DEBUG] = 0x4204,
17241721
[PCIE_INTR2_CPU_BASE] = 0x4300,
17251722
};
@@ -1733,8 +1730,9 @@ static const int pcie_offsets_bcm7425[] = {
17331730
};
17341731

17351732
static const int pcie_offsets_bcm7712[] = {
1733+
[RGR1_SW_INIT_1] = 0x9210,
17361734
[EXT_CFG_INDEX] = 0x9000,
1737-
[EXT_CFG_DATA] = 0x9004,
1735+
[EXT_CFG_DATA] = 0x8000,
17381736
[PCIE_HARD_DEBUG] = 0x4304,
17391737
[PCIE_INTR2_CPU_BASE] = 0x4400,
17401738
};

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