refactor(port_riscv): use "alternate" hexadecimal formatting

yvt · yvt · commit f4e9ce1305ed · 2023-01-14T18:27:08.000+09:00
Ditto.
diff --git a/src/r3_port_riscv/src/threading/imp/instemu.rs b/src/r3_port_riscv/src/threading/imp/instemu.rs
@@ -168,7 +168,7 @@ unsafe fn panic_on_unhandled_exception(fl_state: *mut usize, mcause: usize) -> !
     // Read the original PC from the first-level state
     let pc = unsafe { *fl_state.offset(16) };
 
-    panic!("unhandled exception {mcause} at 0x{pc:08x}");
+    panic!("unhandled exception {mcause} at {pc:#08x}");
 }
 
 #[cfg(not(feature = "emulate-lr-sc"))]

Original file line number	Diff line number	Diff line change
`@@ -168,7 +168,7 @@ unsafe fn panic_on_unhandled_exception(fl_state: *mut usize, mcause: usize) -> !`
`168`	`168`	`// Read the original PC from the first-level state`
`169`	`169`	`let pc = unsafe { *fl_state.offset(16) };`
`170`	`170`
`171`		`- panic!("unhandled exception {mcause} at 0x{pc:08x}");`
	`171`	`+ panic!("unhandled exception {mcause} at {pc:#08x}");`
`172`	`172`	`}`
`173`	`173`
`174`	`174`	`#[cfg(not(feature = "emulate-lr-sc"))]`