test(port_arm): move the UART driver to constance_support_rza1

Author: yvt

Cargo.lock

@@ -32,7 +32,7 @@ output-semihosting = [
 ]
 
 [dependencies]
-constance_support_rza1 = { path = "../constance_support_rza1", optional = true }
+constance_support_rza1 = { path = "../constance_support_rza1", optional = true, features = ["semver-exempt"] }
 constance_port_arm = { path = "../constance_port_arm", optional = true }
 arm_semihosting = { path = "../arm_semihosting", optional = true }
 constance = { path = "../constance", optional = true }

src/constance_port_arm_test_driver/Cargo.toml

@@ -1,5 +1,4 @@
-use core::fmt::Write;
-use rza1::scif0 as scif;
+use constance_support_rza1::serial::ScifExt;
 
 struct Logger;
 
@@ -9,123 +8,28 @@ impl log::Log for Logger {
     }
 
     fn log(&self, record: &log::Record) {
-        let peripherals = unsafe { rza1::Peripherals::steal() };
-
-        interrupt_free(|| {
-            writeln!(
-                SCWriter(&peripherals.SCIF2),
-                "[{:5} {}] {}",
-                record.level(),
-                record.target(),
-                record.args()
-            )
-            .unwrap();
-        });
+        constance_support_rza1::sprintln!(
+            "[{:5} {}] {}",
+            record.level(),
+            record.target(),
+            record.args()
+        );
     }
 
     fn flush(&self) {}
 }
 
-#[derive(Clone, Copy)]
-struct SCWriter<'a>(&'a scif::RegisterBlock);
-
-impl Write for SCWriter<'_> {
-    fn write_str(&mut self, s: &str) -> core::fmt::Result {
-        for &b in s.as_bytes() {
-            self.write_u8(b);
-        }
-        Ok(())
-    }
-}
-
-impl SCWriter<'_> {
-    fn write_u8(self, x: u8) {
-        let sc = self.0;
-        if x == b'\n' {
-            self.write_u8(b'\r');
-        }
-        while sc.fsr.read().tdfe().bit_is_clear() {}
-        sc.ftdr.write(|w| w.d().bits(x));
-        sc.fsr
-            .modify(|_, w| w.tdfe().clear_bit().tend().clear_bit());
-    }
-}
-
 pub fn init() {
-    let peripherals = unsafe { rza1::Peripherals::steal() };
     let rza1::Peripherals {
         CPG, GPIO, SCIF2, ..
-    } = peripherals;
-
-    // Supply clock to SC2
-    CPG.stbcr4.modify(|_, w| w.mstp45().clear_bit());
+    } = unsafe { rza1::Peripherals::steal() };
 
-    // On GR-PEACH, the nets `TGT_[TR]XD` are connected to `P6_[23]`. Configure
-    // `P6_[23]` to use its 7th alternative function - `SC2`.
-    let (mask, shift) = (0b11, 2);
+    SCIF2.enable_clock(&CPG);
+    SCIF2.configure_pins(&GPIO);
+    SCIF2.configure_uart(115200);
 
-    GPIO.pmc6
-        .modify(|_, w| w.pmc62().set_bit().pmc63().set_bit());
-    GPIO.pfcae6
-        .modify(|_, w| w.pfcae62().set_bit().pfcae63().set_bit());
-    GPIO.pfce6
-        .modify(|_, w| w.pfce62().set_bit().pfce63().set_bit());
-    GPIO.pfc6
-        .modify(|_, w| w.pfc62().clear_bit().pfc63().clear_bit());
-    GPIO.pm6
-        .modify(|_, w| w.pm62().set_bit().pm63().clear_bit());
-
-    SCIF2.scr.write(|w| {
-        w.tie()
-            .clear_bit()
-            .rie()
-            .clear_bit()
-            .te()
-            .set_bit()
-            .re()
-            .clear_bit()
-            .reie()
-            .clear_bit()
-            .cke()
-            .internal_sck_in()
-    });
-    SCIF2.smr.write(|w| {
-        w
-            // Asynchronous
-            .ca()
-            .clear_bit()
-            // 8-bit data
-            .chr()
-            .clear_bit()
-            // No parity bits
-            .pe()
-            .clear_bit()
-            // One stop bit
-            .stop()
-            .clear_bit()
-            .cks()
-            .divide_by_1()
-    });
-    // 66.666e6/115200/(64*2**(2*0-1))-1 = 17.0843...
-    SCIF2.brr.write(|w| w.d().bits(17));
+    constance_support_rza1::stdout::set_stdout(SCIF2.into_nb_writer());
 
     log::set_logger(&Logger).unwrap();
     log::set_max_level(log::LevelFilter::Trace);
 }
-
-#[inline]
-fn interrupt_free<T>(x: impl FnOnce() -> T) -> T {
-    let cpsr: u32;
-    unsafe { asm!("mrs {}, cpsr", out(reg)cpsr) };
-    let unmask = (cpsr & (1 << 7)) == 0;
-
-    unsafe { asm!("cpsid i") };
-
-    let ret = x();
-
-    if unmask {
-        unsafe { asm!("cpsie i") };
-    }
-
-    ret
-}

src/constance_port_arm_test_driver/src/logger_rza1_uart.rs

@@ -9,9 +9,20 @@ categories = ["embedded", "no-std"]
 keywords = ["constance", "arm", "renesas"]
 repository = "https://github.com/yvt/Constance"
 
+[features]
+semver-exempt = [
+    "embedded-hal",
+    "rza1/cpg",
+    "rza1/gpio",
+    "rza1/scif",
+    "nb",
+]
+
 [dependencies]
 constance_port_arm = { path = "../constance_port_arm" }
 constance_portkit = { path = "../constance_portkit" }
 constance = { path = "../constance" }
 
+embedded-hal = { version = "0.2.4", optional = true }
 rza1 = { version = "0.2.0", features = ["ostm"] }
+nb = { version = "0.1.2", optional = true }

src/constance_support_rza1/Cargo.toml

@@ -0,0 +1,130 @@
+//! Pin configuration
+// This module is only intended to be used internally, hence the semver
+// exemption. It probably should be in a HAL crate, but there's no HAL crate
+// for RZ/A1.
+#![cfg(feature = "semver-exempt")]
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub enum AltMode {
+    Gpio,
+    Alt1,
+    Alt2,
+    Alt3,
+    Alt4,
+    Alt5,
+    Alt6,
+    Alt7,
+    Alt8,
+}
+
+pub type Pin = (u8, u8);
+
+pub trait GpioExt {
+    /// Configure the alternate function mode of the specified pin.
+    fn set_alt_mode(&self, pin: Pin, mode: AltMode) -> &Self;
+
+    /// Configure the specified pin for output.
+    fn set_output(&self, pin: Pin) -> &Self;
+
+    /// Configure the specified pin for input.
+    fn set_input(&self, pin: Pin) -> &Self;
+}
+
+unsafe fn set_bit16(reg: *mut u16, bit: u8) {
+    unsafe { reg.write_volatile(reg.read_volatile() | (1u16 << bit)) };
+}
+
+unsafe fn clear_bit16(reg: *mut u16, bit: u8) {
+    unsafe { reg.write_volatile(reg.read_volatile() & !(1u16 << bit)) };
+}
+
+#[inline]
+fn panic_if_pin_is_invalid((n, m): Pin) {
+    assert!(n >= 1 && n < 12, "1 <= {} < 12", n);
+    assert!(m < 16, "0 <= {} < 16", m);
+}
+
+impl GpioExt for rza1::gpio::RegisterBlock {
+    #[inline]
+    fn set_alt_mode(&self, (n, m): Pin, mode: AltMode) -> &Self {
+        panic_if_pin_is_invalid((n, m));
+
+        let pmc = (&self.pmc1 as *const _ as *mut u16).wrapping_add((n - 1) as usize * 2);
+        let pfcae = (&self.pfcae1 as *const _ as *mut u16).wrapping_add((n - 1) as usize * 2);
+        let pfce = (&self.pfce1 as *const _ as *mut u16).wrapping_add((n - 1) as usize * 2);
+        let pfc = (&self.pfc1 as *const _ as *mut u16).wrapping_add((n - 1) as usize * 2);
+
+        unsafe {
+            match mode {
+                AltMode::Gpio => {
+                    clear_bit16(pmc, m);
+                }
+                AltMode::Alt1 => {
+                    set_bit16(pmc, m);
+                    clear_bit16(pfcae, m);
+                    clear_bit16(pfce, m);
+                    clear_bit16(pfc, m);
+                }
+                AltMode::Alt2 => {
+                    set_bit16(pmc, m);
+                    clear_bit16(pfcae, m);
+                    clear_bit16(pfce, m);
+                    set_bit16(pfc, m);
+                }
+                AltMode::Alt3 => {
+                    set_bit16(pmc, m);
+                    clear_bit16(pfcae, m);
+                    set_bit16(pfce, m);
+                    clear_bit16(pfc, m);
+                }
+                AltMode::Alt4 => {
+                    set_bit16(pmc, m);
+                    clear_bit16(pfcae, m);
+                    set_bit16(pfce, m);
+                    set_bit16(pfc, m);
+                }
+                AltMode::Alt5 => {
+                    set_bit16(pmc, m);
+                    set_bit16(pfcae, m);
+                    clear_bit16(pfce, m);
+                    clear_bit16(pfc, m);
+                }
+                AltMode::Alt6 => {
+                    set_bit16(pmc, m);
+                    set_bit16(pfcae, m);
+                    clear_bit16(pfce, m);
+                    set_bit16(pfc, m);
+                }
+                AltMode::Alt7 => {
+                    set_bit16(pmc, m);
+                    set_bit16(pfcae, m);
+                    set_bit16(pfce, m);
+                    clear_bit16(pfc, m);
+                }
+                AltMode::Alt8 => {
+                    set_bit16(pmc, m);
+                    set_bit16(pfcae, m);
+                    set_bit16(pfce, m);
+                    set_bit16(pfc, m);
+                }
+            }
+        }
+        self
+    }
+
+    #[inline]
+    fn set_output(&self, (n, m): Pin) -> &Self {
+        panic_if_pin_is_invalid((n, m));
+        let pm = (&self.pm1 as *const _ as *mut u16).wrapping_add((n - 1) as usize * 2);
+        unsafe { clear_bit16(pm, m) };
+        self
+    }
+
+    #[inline]
+    fn set_input(&self, (n, m): Pin) -> &Self {
+        panic_if_pin_is_invalid((n, m));
+        let pm = (&self.pm1 as *const _ as *mut u16).wrapping_add((n - 1) as usize * 2);
+        unsafe { set_bit16(pm, m) };
+        self
+    }
+}

src/constance_support_rza1/src/gpio.rs

@@ -5,6 +5,7 @@
 //! [RZ/A1H]: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
 //! [GR-PEACH]: https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-peach.html
 #![feature(const_fn)]
+#![feature(asm)]
 #![feature(unsafe_block_in_unsafe_fn)] // `unsafe fn` doesn't imply `unsafe {}`
 #![deny(unsafe_op_in_unsafe_fn)]
 #![no_std]
@@ -29,3 +30,7 @@ pub mod os_timer {
 }
 
 pub use self::os_timer::cfg::*;
+
+pub mod gpio;
+pub mod serial;
+pub mod stdout;