Merge branch '✨-riscv-s' into 🦆

`r3_port_riscv` changelog:

> ### Added
>
> - The new option `ThreadingOptions::PRIVILEGE_LEVEL` allows for
>   running the kernel in other privilege levels than M-mode.
> - `use_sbi_timer!` can be used to install a timer driver based on
>   the RISC-V Supervisor Binary Interface.
>
> ### Changed
>
> - Rename `use_timer!` → `use_mtime!`, `TimerOptions` → `MtimeOptions`

Author: yvt

.github/actions/install-qemu/action.yml

@@ -4,7 +4,7 @@ inputs:
   version:
     description: QEMU version to install
     required: true
-    default: 5.1.0
+    default: 6.1.0
   target-list:
     description: List of targets to build
     required: true

.github/workflows/ci.yml

@@ -214,6 +214,10 @@ jobs:
           - { ty: riscv, runner_target: qemu_sifive_u_rv64, runner_args: --arch rv64i+m+a }
           # SiFive U, RV32GC
           - { ty: riscv, runner_target: qemu_sifive_u_rv32, runner_args: "" }
+          # SiFive U, RV64GC, S-mode
+          - { ty: riscv, runner_target: qemu_sifive_u_s_rv64, runner_args: "" }
+          # SiFive U, RV32GC, S-mode
+          - { ty: riscv, runner_target: qemu_sifive_u_s_rv32, runner_args: "" }
           # SiFive E, RV32IMAC
           - { ty: riscv, runner_target: qemu_sifive_e_rv32, runner_args: "" }
           # SiFive E, RV32IA
@@ -231,15 +235,15 @@ jobs:
       - name: Install dependencies (Linux)
         run: |
           sudo apt-get update
-          sudo apt-get install libusb-1.0-0-dev libudev-dev
+          sudo apt-get install libusb-1.0-0-dev libudev-dev ninja-build
 
       - name: Cache QEMU's built binaries
         uses: actions/cache@v2
         with:
           path: ~/.qemu
           key: ${{ runner.os }}-ci-qemu-arm_riscv
 
-      - name: Install QEMU 5.1.0 from source
+      - name: Install QEMU 6.1.0 from source
         uses: ./.github/actions/install-qemu
         with:
           target-list: arm-softmmu,riscv32-softmmu,riscv64-softmmu

Cargo.lock

@@ -41,6 +41,7 @@ The following table shows how to run the kernel test suite for each target.
 | RV32GC          | [SiFive U][] (QEMU)                       | `cargo r3test -t qemu_sifive_u_rv32`                      |
 | RV64IMAC        | SiFive U (QEMU)                           | `cargo r3test -t qemu_sifive_u_rv64 -a rv64i+m+a+c`       |
 | RV64GC          | SiFive U (QEMU)                           | `cargo r3test -t qemu_sifive_u_rv64`                      |
+| RV64GC          | SiFive U (S-mode, QEMU)                   | `cargo r3test -t qemu_sifive_u_s_rv64`                    |
 | RV32IMAC        | [RED-V][] (SPI flash XIP)                 | `cargo r3test -t red_v`                                   |
 | RV64GC          | [Maix][] boards (UART ISP)                | `cargo r3test -t maix`                                    |
 

doc/testing.md

@@ -7,9 +7,19 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## [Unreleased]
 
+### Added
+
+- The new option `ThreadingOptions::PRIVILEGE_LEVEL` allows for running the kernel in other privilege levels than M-mode.
+- `use_sbi_timer!` can be used to install a timer driver based on [the RISC-V Supervisor Binary Interface](https://github.com/riscv-non-isa/riscv-sbi-doc).
+
+### Changed
+
+- Rename `use_timer!` → `use_mtime!`, `TimerOptions` → `MtimeOptions`
+
 ### Fixed
 
 - The default stack alignment (`PortThreading::STACK_ALIGN`) now conforms to the standard ABI requirement (128-bit alignment).
+- The port startup code now calls `<Traits as Timer>::init`.
 
 ## [0.1.3] - 2021-10-29
 

src/r3_port_riscv/CHANGELOG.md

@@ -22,6 +22,8 @@ r3_kernel = { version = "0.0.0", path = "../r3_kernel" }
 r3_core = { version = "0.1.0", path = "../r3_core" }
 
 tock-registers = { version = "0.7.0" }
+unstringify = { version = "0.1.4" }
+seq-macro = { version = "0.3.0" }
 svgbobdoc = { version = "0.3.0-alpha.4" }
 riscv-rt = { version = ">= 0.6.0, < 0.9.0" }
 riscv = { version = ">= 0.5.0, < 0.8.0" }

src/r3_port_riscv/Cargo.toml

@@ -197,4 +197,4 @@ The trap handler stores a first-level state directly below the current stack poi
 
 ## Processor Modes
 
-All code executes in Machine mode. The value of `mstatus.MPP` is always `M` (`0b11`).
+All code executes in Machine mode by default. The value of `mstatus.MPP` is always `M` (`0b11`). Other modes can be selected by [`ThreadingOptions::PRIVILEGE_LEVEL`], which changes all CSRs and CSR values accordingly.

src/r3_port_riscv/src/lib.md

@@ -9,12 +9,14 @@
 #![feature(const_mut_refs)]
 #![feature(const_fn_fn_ptr_basics)]
 #![feature(const_trait_impl)]
+#![feature(generic_const_exprs)]
 #![deny(unsafe_op_in_unsafe_fn)]
 #![deny(unsupported_naked_functions)]
 #![doc(html_logo_url = "https://r3-os.github.io/r3/logo-small.svg")]
 #![doc = include_str!("./lib.md")]
 #![doc = include_str!("./common.md")]
 #![doc = include!("../doc/interrupts.rs")] // `![interrupts]`
+#![recursion_limit = "1024"]
 #![no_std]
 use core::ops::Range;
 use r3_core::kernel::{
@@ -66,17 +68,25 @@ pub mod threading {
     pub mod imp;
 }
 
-/// The standard timer driver.
+/// The `mtime`-based timer driver.
 #[doc(hidden)]
-pub mod timer {
+pub mod mtime {
     pub mod cfg;
     pub mod imp;
 }
 
+/// The SBI-based timer driver.
+#[doc(hidden)]
+pub mod sbi_timer {
+    pub mod cfg;
+    pub mod imp;
+}
+
+pub use self::mtime::cfg::*;
 pub use self::plic::cfg::*;
 pub use self::rt::cfg::*;
+pub use self::sbi_timer::cfg::*;
 pub use self::threading::cfg::*;
-pub use self::timer::cfg::*;
 
 /// Defines the entry points of a port instantiation. Implemented by
 /// [`use_port!`].
@@ -85,7 +95,9 @@ pub trait EntryPoint {
     ///
     /// # Safety
     ///
-    ///  - The processor should be in M-mode and have M-mode interrupts masked.
+    ///  - The processor should be in the privilege mode specified by
+    ///    [`ThreadingOptions::PRIVILEGE_LEVEL`] and have interrupts masked for
+    ///    this privilege level.
     ///  - This method hasn't been entered yet.
     ///
     unsafe fn start() -> !;
@@ -96,15 +108,17 @@ pub trait EntryPoint {
     ///
     /// # Safety
     ///
-    ///  - The processor should be in M-mode and have M-mode interrupts masked.
+    ///  - The processor should be in the privilege mode specified by
+    ///    [`ThreadingOptions::PRIVILEGE_LEVEL`] and have interrupts masked for
+    ///    this privilege level
     ///  - The register state of the background context should be preserved so
     ///    that the handler can restore it later.
     ///
     const TRAP_HANDLER: unsafe extern "C" fn() -> !;
 }
 
 /// An abstract inferface to a port timer driver. Implemented by
-/// [`use_timer!`].
+/// [`use_mtime!`] and [`use_sbi_timer!`].
 pub trait Timer {
     /// Initialize the driver. This will be called just before entering
     /// [`PortToKernel::boot`].

src/r3_port_riscv/src/lib.rs

@@ -1,24 +1,24 @@
-//! The public interface for the RISC-V timer.
+//! The public interface for the `mtime`-based timer driver.
 use r3_core::kernel::InterruptNum;
 
-/// Attach the implementation of [`PortTimer`] that is based on the RISC-V timer
-/// (`mtime`/`mtimecfg`) to a given kernel trait type. This macro also
+/// Attach the implementation of [`PortTimer`] based on the RISC-V machine-mode
+/// timer (`mtime`/`mtimecfg`) to a given kernel trait type. This macro also
 /// implements [`Timer`] on the system type.
-/// **Requires [`TimerOptions`].**
+/// **Requires [`MtimeOptions`].**
 ///
 /// [`PortTimer`]: r3_kernel::PortTimer
 /// [`Timer`]: crate::Timer
 ///
 /// You should do the following:
 ///
-///  - Implement [`TimerOptions`] on the system type `$Traits`.
+///  - Implement [`MtimeOptions`] on the system type `$Traits`.
 ///  - Call `$Traits::configure_timer()` in your configuration function.
 ///    See the following example.
 ///
 /// ```rust,ignore
-/// r3_port_riscv::use_timer!(unsafe impl PortTimer for System);
+/// r3_port_riscv::use_mtime!(unsafe impl PortTimer for System);
 ///
-/// impl r3_port_riscv::TimerOptions for System {
+/// impl r3_port_riscv::MtimeOptions for System {
 ///     const MTIME_PTR: usize = 0x1001_1000;
 ///     const MTIMECMP_PTR: usize = 0x1001_1000;
 ///     const FREQUENCY: u64 = 1_000_000;
@@ -32,10 +32,10 @@ use r3_core::kernel::InterruptNum;
 ///
 /// # Safety
 ///
-///  - `TimerOptions` must be configured correctly.
+///  - `MtimeOptions` must be configured correctly.
 ///
 #[macro_export]
-macro_rules! use_timer {
+macro_rules! use_mtime {
     (unsafe impl PortTimer for $Traits:ty) => {
         const _: () = {
             use $crate::r3_core::{
@@ -44,55 +44,55 @@ macro_rules! use_timer {
             };
             use $crate::r3_kernel::{PortTimer, System, UTicks};
             use $crate::r3_portkit::tickless;
-            use $crate::{timer, Timer, TimerOptions};
+            use $crate::{mtime, MtimeOptions, Timer};
 
             impl PortTimer for $Traits {
                 const MAX_TICK_COUNT: UTicks = u32::MAX;
                 const MAX_TIMEOUT: UTicks = u32::MAX;
 
                 unsafe fn tick_count() -> UTicks {
                     // Safety: We are just forwarding the call
-                    unsafe { timer::imp::tick_count::<Self>() }
+                    unsafe { mtime::imp::tick_count::<Self>() }
                 }
 
                 unsafe fn pend_tick() {
                     // Safety: We are just forwarding the call
-                    unsafe { timer::imp::pend_tick::<Self>() }
+                    unsafe { mtime::imp::pend_tick::<Self>() }
                 }
 
                 unsafe fn pend_tick_after(tick_count_delta: UTicks) {
                     // Safety: We are just forwarding the call
-                    unsafe { timer::imp::pend_tick_after::<Self>(tick_count_delta) }
+                    unsafe { mtime::imp::pend_tick_after::<Self>(tick_count_delta) }
                 }
             }
 
             impl Timer for $Traits {
                 unsafe fn init() {
-                    unsafe { timer::imp::init::<Self>() }
+                    unsafe { mtime::imp::init::<Self>() }
                 }
             }
 
             const TICKLESS_CFG: tickless::TicklessCfg =
                 match tickless::TicklessCfg::new(tickless::TicklessOptions {
-                    hw_freq_num: <$Traits as TimerOptions>::FREQUENCY,
-                    hw_freq_denom: <$Traits as TimerOptions>::FREQUENCY_DENOMINATOR,
-                    hw_headroom_ticks: <$Traits as TimerOptions>::HEADROOM,
+                    hw_freq_num: <$Traits as MtimeOptions>::FREQUENCY,
+                    hw_freq_denom: <$Traits as MtimeOptions>::FREQUENCY_DENOMINATOR,
+                    hw_headroom_ticks: <$Traits as MtimeOptions>::HEADROOM,
                     // `mtime` is a 64-bit free-running counter and it is
                     // expensive to create a 32-bit timer with an arbitrary
                     // period out of it.
                     force_full_hw_period: true,
                     // If clearing `mtime` is not allowed, we must record the
                     // starting value of `mtime` by calling `reset`.
-                    resettable: !<$Traits as TimerOptions>::RESET_MTIME,
+                    resettable: !<$Traits as MtimeOptions>::RESET_MTIME,
                 }) {
                     Ok(x) => x,
                     Err(e) => e.panic(),
                 };
 
             static mut TIMER_STATE: tickless::TicklessState<TICKLESS_CFG> = Init::INIT;
 
-            // Safety: Only `use_timer!` is allowed to `impl` this
-            unsafe impl timer::imp::TimerInstance for $Traits {
+            // Safety: Only `use_mtime!` is allowed to `impl` this
+            unsafe impl mtime::imp::TimerInstance for $Traits {
                 const TICKLESS_CFG: tickless::TicklessCfg = TICKLESS_CFG;
 
                 type TicklessState = tickless::TicklessState<TICKLESS_CFG>;
@@ -107,15 +107,15 @@ macro_rules! use_timer {
                 where
                     C: ~const traits::CfgInterruptLine<System = System<Self>>,
                 {
-                    timer::imp::configure(b);
+                    mtime::imp::configure(b);
                 }
             }
         };
     };
 }
 
-/// The options for [`use_timer!`].
-pub trait TimerOptions {
+/// The options for [`use_mtime!`].
+pub trait MtimeOptions {
     /// The memory address of the `mtime` register.
     const MTIME_PTR: usize;