test(port_arm_m): support benchmark tests on RP2040

The measured cycle counts are somewhat higher than those of
`nucleo_f401re` (Cortex-M4F) by about 10%.

Author: yvt

src/r3_port_arm_m_test_driver/src/board_rp2040.rs

@@ -11,6 +11,8 @@ pub mod mux {
     pub const BEGIN_LOG: &str = "\x172";
 }
 
+pub const SYSTICK_FREQUENCY: u64 = 48_000_000;
+
 #[panic_handler]
 fn panic(info: &PanicInfo) -> ! {
     // Disable IRQ
@@ -29,6 +31,12 @@ pub fn enter_poll_loop() -> ! {
     }
 }
 
+/// Implements `kernel_benchmarks::Driver::performance_time`.
+pub fn performance_time() -> u32 {
+    let timerawl = unsafe { (0x40054028 as *const u32).read_volatile() };
+    timerawl.wrapping_mul(2) // scale by `tick.cycles`
+}
+
 struct Logger;
 
 impl log::Log for Logger {
@@ -69,6 +77,22 @@ pub const fn configure<System: Kernel>(b: &mut CfgBuilder<System>) {
                 &p.WATCHDOG,
             );
 
+            // clk_ref → clk_sys = 48MHz
+            p.CLOCKS.clk_sys_ctrl.modify(|_, w| w.src().clk_ref());
+
+            // Supply clk_ref / 2 = 24MHz to SysTick, watchdog, and timer
+            // because we want to measure times at high precision in
+            // benchmarks. Setting `cycles = 1` would be ideal but doesn't work
+            // for some reason.
+            p.WATCHDOG
+                .tick
+                .write(|b| unsafe { b.cycles().bits(2).enable().set_bit() });
+
+            // Reset the timer used by `performance_time`
+            p.RESETS.reset.modify(|_, w| w.timer().set_bit());
+            p.RESETS.reset.modify(|_, w| w.timer().clear_bit());
+            while p.RESETS.reset_done.read().timer().bit_is_clear() {}
+
             // Reset and enable IO bank 0
             p.RESETS
                 .reset

src/r3_port_arm_m_test_driver/src/main.rs

@@ -73,8 +73,12 @@ macro_rules! instantiate_test {
         }
 
         impl port::SysTickOptions for System {
+            #[cfg(feature = "board-rp_pico")]
+            const FREQUENCY: u64 = board_rp2040::SYSTICK_FREQUENCY;
+
             // STM32F401
             // SysTick = AHB/8, AHB = HSI (internal 16-MHz RC oscillator)
+            #[cfg(not(feature = "board-rp_pico"))]
             const FREQUENCY: u64 = 2_000_000;
         }
 
@@ -88,10 +92,17 @@ macro_rules! instantiate_test {
             fn success() {
                 report_success();
             }
+
+            #[cfg(not(feature = "board-rp_pico"))]
             fn performance_time() -> u32 {
                 cortex_m::peripheral::DWT::get_cycle_count()
             }
 
+            #[cfg(feature = "board-rp_pico")]
+            fn performance_time() -> u32 {
+                board_rp2040::performance_time()
+            }
+
             const PERFORMANCE_TIME_UNIT: &'static str = "cycle(s)";
 
             // Most targets should have at least four interrupt lines
@@ -125,6 +136,7 @@ macro_rules! instantiate_test {
         const fn configure_app(b: &mut CfgBuilder<System>) -> test_case::App<System> {
             // Configure DWT for performance measurement
             #[cfg(feature = "kernel_benchmarks")]
+            #[cfg(not(feature = "board-rp_pico"))]
             StartupHook::<System>::build().start(|_| {
                 unsafe {
                     let mut peripherals = cortex_m::peripheral::Peripherals::steal();