Merge branch '✨-rza1' into 🦆

Author: yvt

Cargo.lock

@@ -13,6 +13,7 @@ members = [
     "src/constance_port_riscv_test_driver",
     "src/constance_port_std",
     "src/constance_portkit",
+    "src/constance_support_rza1",
     "src/constance_test_runner",
     "src/constance_test_suite",
 ]

Cargo.toml

@@ -129,6 +129,10 @@ cd examples/basic_nucleo_f401re
 cargo embed --release
 ```
 
+See [this document](examples/basic_gr_peach/README.md) for how to run the example application on [the GR-PEACH development board].
+
+[the GR-PEACH development board]: https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-peach.html#overview
+
 ## Prerequisites
 
 You need a Nightly Rust compiler. This project is heavily reliant on unstable features, so it might or might not work with a newer compiler version. See the file `rust-toolchain` to find out which compiler version this project is currently tested with.
@@ -150,10 +154,13 @@ In this case, you need to run `rustup target add thumbv7m-none-eabi`.
  - [rustup], which will automatically install the version of Nightly Rust compiler specified by `rust-toolchain`
  - [QEMU](https://www.qemu.org/) 4.2 or later to test the Arm-M/-A port.
  - libusb 1.x to test the Arm-M/-A port.
+ - [OpenOCD](http://openocd.org) to test the Arm-A port on GR-PEACH.
+ - `JLinkExe`<sup>†</sup> from [J-Link Software] to test the RISC-V port on RED-V.
 
 [rustup]: https://rustup.rs/
+[J-Link Software]: https://www.segger.com/downloads/jlink#J-LinkSoftwareAndDocumentationPack
 
-[Nix] users can use the provided `shell.nix` file to install all required software.
+[Nix] users can use the provided `shell.nix` file to install all required software except for those marked with <sup>†</sup>.
 
 [Nix]: https://nixos.org/nix/
 
@@ -163,6 +170,7 @@ In this case, you need to run `rustup target add thumbv7m-none-eabi`.
  - The Armv7-M port and NUCLEO-F401RE: `cargo run -p constance_test_runner -- -t nucleo_f401re`
  - The Armv7-M port and Arm MPS2+ AN385 (QEMU emulation): `cargo run -p constance_test_runner -- -t qemu_mps2_an385`
  - The Armv6-M port and Arm MPS2+ AN385 (QEMU emulation): `cargo run -p constance_test_runner -- -t qemu_mps2_an385_v6m`
+ - The Armv7-A port and GR-PEACH: `cargo run -p constance_test_runner -- -t gr_peach`
  - The Armv7-A port and Arm RealView Platform Baseboard Explore for Cortex-A9 (QEMU emulation): `cargo run -p constance_test_runner -- -t qemu_realview_pbx_a9`
  - The RISC-V port and SiFive E (QEMU emulation): `cargo run -p constance_test_runner -- -t qemu_sifive_e`
  - The RISC-V port and RED-V (SPI flash XIP): `cargo run -p constance_test_runner -- -t red_v`
@@ -173,4 +181,5 @@ The `-b` option instructs `constance_test_runner` to run benchmark tests. Note t
 
  - Hosted platform: `cargo bench -p constance_port_std`
  - The Armv7-M port and NUCLEO-F401RE: `cargo run -p constance_test_runner -- -t nucleo_f401re -b`
+ - The Armv7-A port and GR-PEACH: `cargo run -p constance_test_runner -- -t gr_peach -b`
  - The RISC-V port and RED-V (SPI flash XIP): `cargo run -p constance_test_runner -- -t red_v -b`

README.md

@@ -0,0 +1,9 @@
+target remote :3333
+mon reset halt
+
+# Enable the on-chip RAM
+mon mwb 0xFCFE0400 0xff
+mon mwb 0xFCFE0404 0xff
+mon mwb 0xFCFE0408 0xff
+
+load

examples/basic_gr_peach/.gdbinit

@@ -5,7 +5,9 @@ authors = ["yvt <i@yvt.jp>"]
 edition = "2018"
 
 [dependencies]
+constance_support_rza1 = { path = "../../src/constance_support_rza1", features = ["semver-exempt"] }
 constance_port_arm = { path = "../../src/constance_port_arm" }
 constance = { path = "../../src/constance" }
 
 rtt-target = { version = "0.2.0" }
+rza1 = { version = "0.2.0", features = ["cpg", "gpio", "scif"] }

examples/basic_gr_peach/Cargo.toml

@@ -0,0 +1,38 @@
+This directory contains an example Constance application for [GR-PEACH].
+
+[GR-PEACH]: https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-peach.html#overview
+
+You need the following software to perform the steps described in this document:
+
+ - [OpenOCD]
+ - `arm-none-eabi-gdb`
+ - [rustup] or the correct version of the Rust toolchain
+ - The Armv7-A build of the Rust standard library (can be [installed] by `rustup target add armv7a-none-eabi`)
+
+[OpenOCD]: http://openocd.org
+[rustup]: https://rustup.rs
+[installed]: https://rust-lang.github.io/rustup/cross-compilation.html
+
+We are going to load this application onto the target using OpenOCD and GDB. In one terminal window, start an instance of OpenOCD using the supplied configuration file:
+
+```shell
+openocd -f opencd.cfg
+```
+
+In another terminal window, compile and load the application by doing the following:
+
+```shell
+cargo build --release
+arm-none-eabi-gdb -iex 'target remote localhost:3333' ../../target/armv7a-none-eabi/release/basic_gr_peach
+```
+
+GDB automatically executes the commands in the `.gdbinit` file to download the image to the target's on-chip memory and direct PC to the entry point. Now, open a serial terminal application, configure the baud rate to 115200, and enter `c` in GDB. You should see the following output in the serial terminal:
+
+```text
+UART is ready
+COTTAGE = Objects { task1: Task(1), task2: Task(2) }
+time = 5.178ms
+time = 1.006644s
+time = 2.007444s
+...
+```

examples/basic_gr_peach/README.md

@@ -0,0 +1,17 @@
+source [find interface/cmsis-dap.cfg]
+source [find target/swj-dp.tcl]
+
+set _CHIPNAME rza1
+swj_newdap $_CHIPNAME cpu -expected-id 0x3ba02477
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_TARGETNAME
+
+adapter_khz 1000
+reset_config trst_and_srst
+debug_level 0
+gdb_target_description enable
+gdb_breakpoint_override hard
+init
+halt
+cortex_a dbginit

examples/basic_gr_peach/openocd.cfg

@@ -7,14 +7,17 @@
 #![no_std]
 #![no_main]
 #![cfg(target_os = "none")]
+#![recursion_limit = "1000"] // probably because of large interrupt numbers
 
 // -----------------------------------------------------------------------
 
 use constance_port_arm as port;
+use constance_support_rza1 as support_rza1;
 
 port::use_port!(unsafe struct System);
 port::use_startup!(unsafe System);
 port::use_gic!(unsafe impl PortInterrupts for System);
+support_rza1::use_os_timer!(unsafe impl PortTimer for System);
 
 impl port::ThreadingOptions for System {}
 
@@ -35,26 +38,19 @@ impl port::GicOptions for System {
     const GIC_CPU_BASE: usize = 0xe8202000;
 }
 
-impl constance::kernel::PortTimer for System {
-    // TODO
-    const MAX_TICK_COUNT: constance::kernel::UTicks = 0xffffffff;
-    const MAX_TIMEOUT: constance::kernel::UTicks = 0x80000000;
-    unsafe fn tick_count() -> constance::kernel::UTicks {
-        0
-    }
+impl support_rza1::OsTimerOptions for System {
+    const FREQUENCY: u64 = 33_333_000;
 }
 
-impl port::Timer for System {}
-
 // -----------------------------------------------------------------------
 
 use constance::{
     kernel::{cfg::CfgBuilder, StartupHook, Task},
     prelude::*,
 };
 
-// Install a global panic handler that uses RTT
-mod panic_rtt_target;
+// Install a global panic handler that uses the serial port
+mod panic_serial;
 
 #[derive(Debug)]
 struct Objects {
@@ -67,28 +63,25 @@ const COTTAGE: Objects = constance::build!(System, configure_app => Objects);
 const fn configure_app(b: &mut CfgBuilder<System>) -> Objects {
     b.num_task_priority_levels(4);
 
-    // Initialize RTT (Real-Time Transfer) with a single up channel and set
-    // it as the print channel for the printing macros
+    System::configure_os_timer(b);
+
+    // Initialize the serial port
     StartupHook::build()
         .start(|_| {
-            let channels = rtt_target::rtt_init! {
-                up: {
-                    0: {
-                        size: 1024
-                        mode: NoBlockSkip
-                        name: "Terminal"
-                    }
-                }
-            };
-
-            unsafe {
-                rtt_target::set_print_channel_cs(
-                    channels.up.0,
-                    &((|arg, f| f(arg)) as rtt_target::CriticalSectionFunc),
-                )
-            };
-
-            rtt_target::rprintln!("RTT is ready");
+            use support_rza1::serial::ScifExt;
+
+            #[allow(non_snake_case)]
+            let rza1::Peripherals {
+                CPG, GPIO, SCIF2, ..
+            } = unsafe { rza1::Peripherals::steal() };
+
+            SCIF2.enable_clock(&CPG);
+            SCIF2.configure_pins(&GPIO);
+            SCIF2.configure_uart(115200);
+
+            support_rza1::stdout::set_stdout(SCIF2.into_nb_writer());
+
+            support_rza1::sprintln!("UART is ready");
         })
         .finish(b);
 
@@ -103,14 +96,14 @@ const fn configure_app(b: &mut CfgBuilder<System>) -> Objects {
 }
 
 fn task1_body(_: usize) {
-    rtt_target::rprintln!("COTTAGE = {:?}", COTTAGE);
+    support_rza1::sprintln!("COTTAGE = {:?}", COTTAGE);
 
     COTTAGE.task2.activate().unwrap();
 }
 
 fn task2_body(_: usize) {
     loop {
-        rtt_target::rprintln!("time = {:?}", System::time().unwrap());
+        support_rza1::sprintln!("time = {:?}", System::time().unwrap());
         System::sleep(constance::time::Duration::from_secs(1)).unwrap();
     }
 }

examples/basic_gr_peach/src/main.rs

@@ -0,0 +1,14 @@
+use constance_support_rza1::sprintln;
+use core::panic::PanicInfo;
+
+// Install a global panic handler that uses the serial port
+#[inline(never)]
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    // Disable IRQ
+    unsafe { llvm_asm!("cpsid i"::::"volatile") };
+
+    sprintln!("{}", info);
+
+    loop {}
+}