fix(examples): enforce 256-byte alignment on exception vector table for Cortex-M0+

Cortex-M0+ Technical Reference Manual:

> If implemented, the VTOR enables bits[31:8] of the vector table
> address to be specified.

Fixes `smp_rp_pico` misbehaving depending on seemingly unknown factors.

Author: yvt

examples/smp_rp_pico/src/core1.rs

@@ -86,7 +86,9 @@ unsafe extern "C" fn core1_entry() -> ! {
     unsafe { <SystemTraits as port::EntryPoint>::start() }
 }
 
-#[repr(C, align(128))]
+// Cortex-M0+ Technical Reference Manual: “If implemented, the VTOR enables
+// bits[31:8] of the vector table address to be specified.”
+#[repr(C, align(256))]
 struct VectorTable<T>(T);
 
 static CORE1_VECTOR_TABLE: VectorTable<[unsafe extern "C" fn(); 48]> = {