test(port_arm): implement kernel_benchmarks::Driver::performance_time using PMU cycle counter

The kernel benchmark tests can now run on GR-PEACH.

Author: yvt

README.md

@@ -177,4 +177,5 @@ The `-b` option instructs `constance_test_runner` to run benchmark tests. Note t
 
  - Hosted platform: `cargo bench -p constance_port_std`
  - The Armv7-M port and NUCLEO-F401RE: `cargo run -p constance_test_runner -- -t nucleo_f401re -b`
+ - The Armv7-A port and GR-PEACH: `cargo run -p constance_test_runner -- -t gr_peach -b`
  - The RISC-V port and RED-V (SPI flash XIP): `cargo run -p constance_test_runner -- -t red_v -b`

src/constance_port_arm_test_driver/src/main.rs

@@ -24,6 +24,9 @@ mod logger_semihosting;
 #[cfg(feature = "output-semihosting")]
 mod panic_semihosting;
 
+#[cfg(feature = "kernel_benchmarks")]
+mod pmu;
+
 #[allow(unused_macros)]
 macro_rules! instantiate_test {
     // If a test case is specified, instantiate the test case
@@ -129,12 +132,11 @@ macro_rules! instantiate_test {
             }
 
             fn performance_time() -> u32 {
-                // SP804 Timer1
-                !unsafe { ((<System as port::Sp804Options>::SP804_BASE + 4)
-                    as *const u32).read_volatile() }
+                use register::cpu::RegisterReadWrite;
+                pmu::PMCCNTR.get()
             }
 
-            const PERFORMANCE_TIME_UNIT: &'static str = "μs";
+            const PERFORMANCE_TIME_UNIT: &'static str = "CPU cycles";
 
             // Chose PPIs.
             // SGIs (software-generated interrupts) don't support disabling.
@@ -171,6 +173,14 @@ macro_rules! instantiate_test {
             #[cfg(feature = "board-rza1")]
             System::configure_os_timer(b);
 
+            // Start PMU cycle counter
+            #[cfg(feature = "kernel_benchmarks")]
+            StartupHook::build().start(|_| {
+                use register::cpu::RegisterReadWrite;
+                pmu::PMCR.modify(pmu::PMCR::E::SET + pmu::PMCR::D::DivideBy1);
+                pmu::PMCNTENSET.modify(pmu::PMCNTENSET::C::SET);
+            }).finish(b);
+
             // Redirect the log output to stderr
             #[cfg(all(feature = "output-semihosting", not(feature = "board-rza1")))]
             StartupHook::build().start(|_| {

src/constance_port_arm_test_driver/src/pmu.rs

@@ -0,0 +1,82 @@
+//! Arm PMU
+macro_rules! sys_coproc_read_raw {
+    ($width:ty, [$cp:ident, $crn:ident, $opc1:literal, $crm:ident, $opc2:literal]) => {
+        #[inline]
+        fn get(&self) -> u32 {
+            let reg;
+            unsafe {
+                asm!(
+                    concat!(
+                        "mrc ", stringify!($cp), ", ", stringify!($opc1), ", {}, ",
+                        stringify!($crn), ", ", stringify!($crm), ", ", stringify!($opc2)
+                    ),
+                    out(reg)reg,
+                );
+            }
+            reg
+        }
+    };
+}
+/// Implements `register::cpu::RegisterReadWrite::set`.
+macro_rules! sys_coproc_write_raw {
+    ($width:ty, [$cp:ident, $crn:ident, $opc1:literal, $crm:ident, $opc2:literal]) => {
+        #[inline]
+        fn set(&self, value: u32) {
+            unsafe {
+                asm!(
+                    concat!(
+                        "mcr ", stringify!($cp), ", ", stringify!($opc1), ", {}, ",
+                        stringify!($crn), ", ", stringify!($crm), ", ", stringify!($opc2)
+                    ),
+                    in(reg)value,
+                );
+            }
+        }
+    };
+}
+
+register::register_bitfields! {u32,
+    pub PMCNTENSET [
+        /// PMCCNTR enable bit.
+        C OFFSET(31) NUMBITS(1) []
+    ]
+}
+
+/// Performance Monitors Count Enable Set register
+pub const PMCNTENSET: PMCNTENSETAccessor = PMCNTENSETAccessor;
+pub struct PMCNTENSETAccessor;
+
+impl register::cpu::RegisterReadWrite<u32, PMCNTENSET::Register> for PMCNTENSETAccessor {
+    sys_coproc_read_raw!(u32, [p15, c9, 0, c12, 1]);
+    sys_coproc_write_raw!(u32, [p15, c9, 0, c12, 1]);
+}
+
+register::register_bitfields! {u32,
+    pub PMCR [
+        /// Clock divider.
+        D OFFSET(3) NUMBITS(1) [
+            DivideBy1 = 0,
+            DivideBy64 = 1
+        ],
+        /// Enable.
+        E OFFSET(0) NUMBITS(1) []
+    ]
+}
+
+///  Performance Monitors Control Register
+pub const PMCR: PMCRAccessor = PMCRAccessor;
+pub struct PMCRAccessor;
+
+impl register::cpu::RegisterReadWrite<u32, PMCR::Register> for PMCRAccessor {
+    sys_coproc_read_raw!(u32, [p15, c9, 0, c12, 0]);
+    sys_coproc_write_raw!(u32, [p15, c9, 0, c12, 0]);
+}
+
+/// Performance Monitors Cycle Count Register
+pub const PMCCNTR: PMCCNTRAccessor = PMCCNTRAccessor;
+pub struct PMCCNTRAccessor;
+
+impl register::cpu::RegisterReadWrite<u32, ()> for PMCCNTRAccessor {
+    sys_coproc_read_raw!(u32, [p15, c9, 0, c13, 0]);
+    sys_coproc_write_raw!(u32, [p15, c9, 0, c13, 0]);
+}