@@ -319,12 +319,6 @@ class I2SDriverESP32V1 {
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(i2s_slot_mode_t )cfg.channels );
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}
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- i2s_pdm_rx_slot_config_t getRxSlotConfig (I2SConfigESP32V1 &cfg) {
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- return I2S_PDM_RX_SLOT_DEFAULT_CONFIG (
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- (i2s_data_bit_width_t )cfg.bits_per_sample ,
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- (i2s_slot_mode_t )cfg.channels );
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- }
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-
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i2s_chan_config_t getChannelConfig (I2SConfigESP32V1 &cfg) {
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return I2S_CHANNEL_DEFAULT_CONFIG (
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(i2s_port_t )cfg.port_no ,
@@ -335,10 +329,6 @@ class I2SDriverESP32V1 {
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return I2S_PDM_TX_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
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}
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- i2s_pdm_rx_clk_config_t getRxClockConfig (I2SConfigESP32V1 &cfg) {
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- return I2S_PDM_RX_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
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- }
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-
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bool startTX (I2SConfigESP32V1 &cfg, i2s_chan_handle_t &tx_chan, int txPin) {
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i2s_pdm_tx_config_t pdm_tx_cfg = {
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.clk_cfg = getTxClockConfig (cfg),
@@ -365,6 +355,15 @@ class I2SDriverESP32V1 {
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return true ;
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}
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+ #if defined(USE_PDM_RX)
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+ i2s_pdm_rx_slot_config_t getRxSlotConfig (I2SConfigESP32V1 &cfg) {
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+ return I2S_PDM_RX_SLOT_DEFAULT_CONFIG (
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+ (i2s_data_bit_width_t )cfg.bits_per_sample ,
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+ (i2s_slot_mode_t )cfg.channels );
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+ }
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+ i2s_pdm_rx_clk_config_t getRxClockConfig (I2SConfigESP32V1 &cfg) {
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+ return I2S_PDM_RX_CLK_DEFAULT_CONFIG ((uint32_t )cfg.sample_rate );
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+ }
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bool startRX (I2SConfigESP32V1 &cfg, i2s_chan_handle_t &rx_chan, int rxPin) {
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i2s_pdm_rx_config_t pdm_rx_cfg = {
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.clk_cfg = getRxClockConfig (cfg),
@@ -390,7 +389,12 @@ class I2SDriverESP32V1 {
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}
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return true ;
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}
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-
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+ #else
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+ bool startRX (I2SConfigESP32V1 &cfg, i2s_chan_handle_t &rx_chan, int rxPin) {
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+ LOGE (" PDM RX not supported" );
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+ return false ;
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+ }
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+ #endif
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} pdm;
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#endif
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