Merge branch 'espressif:master' into pioarduino

Jason2866 · web-flow · commit e13d573b507b · 2024-10-22T18:41:55.000+02:00
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -297,6 +297,8 @@ target_esp32s2_usbcdc:
   extends: .target_esptool_test
   tags:
     - esptool_esp32s2_cdc_target
+  variables:
+    ESPTOOL_TEST_USB_OTG: "1"
   script:
     - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32S2_USBCDC --chip esp32s2 --baud 115200
 
@@ -347,6 +349,8 @@ target_esp32s3_usbcdc:
   extends: .target_esptool_test
   tags:
     - esptool_esp32s3_cdc_target
+  variables:
+    ESPTOOL_TEST_USB_OTG: "1"
   script:
     - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32S3_USBCDC --chip esp32s3 --baud 115200
 
diff --git a/docs/en/esptool/advanced-options.rst b/docs/en/esptool/advanced-options.rst
@@ -31,8 +31,8 @@ The ``--after`` argument allows you to specify whether the chip should be reset
 
 .. list::
 
-    * ``--after hard_reset`` is the default. The DTR serial control line is used to reset the chip into a normal boot sequence.
-    :esp8266:* ``--after soft_reset`` This runs the user firmware, but any subsequent reset will return to the serial bootloader. This was the reset behaviour in esptool v1.x.
+    * ``--after hard_reset`` is the default. The RTS serial control line is used to reset the chip into a normal boot sequence.
+    :esp8266: * ``--after soft_reset`` runs the user firmware, but any subsequent reset will return to the serial bootloader. This was the reset behaviour in esptool v1.x.
     * ``--after no_reset`` leaves the chip in the serial bootloader, no reset is performed.
     * ``--after no_reset_stub`` leaves the chip in the stub bootloader, no reset is performed.
 
diff --git a/docs/en/esptool/configuration-file.rst b/docs/en/esptool/configuration-file.rst
@@ -111,14 +111,19 @@ Complete list of configurable options:
 +------------------------------+-----------------------------------------------------------+----------+
 | custom_reset_sequence        | Custom reset sequence for resetting into the bootloader   |          |
 +------------------------------+-----------------------------------------------------------+----------+
+| custom_hard_reset_sequence   | Custom reset sequence for hard resetting the chip         |          |
++------------------------------+-----------------------------------------------------------+----------+
 
-Custom Reset Sequence
----------------------
+Custom Reset Sequences
+----------------------
 
 The ``custom_reset_sequence`` configuration option allows you to define a reset sequence which will get
 used when an :ref:`automatic reset into the serial bootloader <automatic-bootloader>` is performed.
 
-The sequence is defined with a string in the following format:
+The ``custom_hard_reset_sequence`` option allows you to define a reset sequence which will get
+used when a hard reset (a reset out of the bootloader) is performed.
+
+A sequence is defined with a string in the following format:
 
 - Consists of individual commands divided by ``|`` (e.g. ``R0|D1|W0.5``).
 - Commands (e.g. ``R0``) are defined by a code (``R``) and an argument (``0``).
@@ -148,3 +153,11 @@ For example: ``D0|R1|W0.1|D1|R0|W0.5|D0`` represents the following classic reset
     _setRTS(False)  # EN=HIGH, chip out of reset
     time.sleep(0.05)
     _setDTR(False)  # IO0=HIGH, done
+
+Similarly, ``R1|W0.1|R0`` represents the classic hard reset sequence:
+
+.. code-block:: python
+
+    _setRTS(True)   # EN=LOW, chip in reset
+    time.sleep(0.1)
+    _setRTS(False)  # EN=HIGH, chip out of reset
diff --git a/esp_rfc2217_server/esp_port_manager.py b/esp_rfc2217_server/esp_port_manager.py
@@ -74,7 +74,11 @@ def _hard_reset_thread(self):
         """
         if self.logger:
             self.logger.info("Activating hard reset in thread")
-        HardReset(self.serial)()
+        cfg_custom_hard_reset_sequence = cfg.get("custom_hard_reset_sequence")
+        if cfg_custom_hard_reset_sequence is not None:
+            CustomReset(self.serial, cfg_custom_hard_reset_sequence)()
+        else:
+            HardReset(self.serial)()
 
     def _reset_thread(self):
         """
diff --git a/esptool/__init__.py b/esptool/__init__.py
@@ -18,6 +18,7 @@
     "merge_bin",
     "read_flash",
     "read_flash_status",
+    "read_flash_sfdp",
     "read_mac",
     "read_mem",
     "run",
diff --git a/esptool/config.py b/esptool/config.py
@@ -21,6 +21,7 @@
     "reset_delay",
     "open_port_attempts",
     "custom_reset_sequence",
+    "custom_hard_reset_sequence",
 ]
 
 
diff --git a/esptool/loader.py b/esptool/loader.py
@@ -1525,9 +1525,13 @@ def get_crystal_freq(self):
             )
         return norm_xtal
 
-    def hard_reset(self):
+    def hard_reset(self, uses_usb=False):
         print("Hard resetting via RTS pin...")
-        HardReset(self._port)()
+        cfg_custom_hard_reset_sequence = cfg.get("custom_hard_reset_sequence")
+        if cfg_custom_hard_reset_sequence is not None:
+            CustomReset(self._port, cfg_custom_hard_reset_sequence)()
+        else:
+            HardReset(self._port, uses_usb)()
 
     def soft_reset(self, stay_in_bootloader):
         if not self.IS_STUB:
diff --git a/esptool/reset.py b/esptool/reset.py
@@ -205,5 +205,5 @@ def _parse_string_to_seq(self, seq_str):
             cmds = seq_str.split("|")
             fn_calls_list = [self.format_dict[cmd[0]].format(cmd[1:]) for cmd in cmds]
         except Exception as e:
-            raise FatalError(f'Invalid "custom_reset_sequence" option format: {e}')
+            raise FatalError(f"Invalid custom reset sequence option format: {e}")
         return "\n".join(fn_calls_list)
diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# SPDX-FileCopyrightText: 2014-2024 Fredrik Ahlberg, Angus Gratton,
 # Espressif Systems (Shanghai) CO LTD, other contributors as noted.
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
@@ -63,6 +63,12 @@ class ESP32C2ROM(ESP32C3ROM):
         [0x4037C000, 0x403C0000, "IRAM"],
     ]
 
+    RTCCNTL_BASE_REG = 0x60008000
+    RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0084
+    RTC_CNTL_WDTCONFIG1_REG = RTCCNTL_BASE_REG + 0x0088
+    RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x009C
+    RTC_CNTL_WDT_WKEY = 0x50D83AA1
+
     UF2_FAMILY_ID = 0x2B88D29C
 
     KEY_PURPOSES: Dict[int, str] = {}
@@ -130,6 +136,9 @@ def _post_connect(self):
             self.stub_is_disabled = True
             self.IS_STUB = False
 
+    def hard_reset(self):
+        ESPLoader.hard_reset(self)
+
     """ Try to read (encryption key) and check if it is valid """
 
     def is_flash_encryption_key_valid(self):
diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# SPDX-FileCopyrightText: 2014-2024 Fredrik Ahlberg, Angus Gratton,
 # Espressif Systems (Shanghai) CO LTD, other contributors as noted.
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
@@ -83,6 +83,7 @@ class ESP32C3ROM(ESP32ROM):
     RTC_CNTL_SWD_WKEY = 0x8F1D312A
 
     RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090
+    RTC_CNTL_WDTCONFIG1_REG = RTCCNTL_BASE_REG + 0x0094
     RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00A8
     RTC_CNTL_WDT_WKEY = 0x50D83AA1
 
@@ -252,6 +253,21 @@ def _post_connect(self):
         if not self.sync_stub_detected:  # Don't run if stub is reused
             self.disable_watchdogs()
 
+    def hard_reset(self):
+        if self.uses_usb_jtag_serial():
+            self.rtc_wdt_reset()
+        else:
+            ESPLoader.hard_reset(self)
+
+    def rtc_wdt_reset(self):
+        print("Hard resetting with RTC WDT...")
+        self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
+        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000)  # set WDT timeout
+        self.write_reg(
+            self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
+        )  # enable WDT
+        self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)  # lock
+
     def check_spi_connection(self, spi_connection):
         if not set(spi_connection).issubset(set(range(0, 22))):
             raise FatalError("SPI Pin numbers must be in the range 0-21.")
diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py
@@ -8,7 +8,6 @@
 
 from .esp32c6 import ESP32C6ROM
 from ..loader import ESPLoader
-from ..reset import HardReset
 from ..util import FatalError
 
 
@@ -128,8 +127,7 @@ def get_crystal_freq_rom_expect(self):
         ) >> self.PCR_SYSCLK_XTAL_FREQ_S
 
     def hard_reset(self):
-        print("Hard resetting via RTS pin...")
-        HardReset(self._port, self.uses_usb_jtag_serial())()
+        ESPLoader.hard_reset(self, self.uses_usb_jtag_serial())
 
     def change_baud(self, baud):
         if not self.IS_STUB:
diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022 Fredrik Ahlberg, Angus Gratton,
+# SPDX-FileCopyrightText: 2024 Fredrik Ahlberg, Angus Gratton,
 # Espressif Systems (Shanghai) CO LTD, other contributors as noted.
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
@@ -72,6 +72,7 @@ class ESP32C6ROM(ESP32C3ROM):
 
     DR_REG_LP_WDT_BASE = 0x600B1C00
     RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0  # LP_WDT_RWDT_CONFIG0_REG
+    RTC_CNTL_WDTCONFIG1_REG = DR_REG_LP_WDT_BASE + 0x0004  # LP_WDT_RWDT_CONFIG1_REG
     RTC_CNTL_WDTWPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0018  # LP_WDT_RWDT_WPROTECT_REG
 
     RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x001C  # LP_WDT_SWD_CONFIG_REG
diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py
@@ -1,11 +1,12 @@
-# SPDX-FileCopyrightText: 2022 Fredrik Ahlberg, Angus Gratton,
+# SPDX-FileCopyrightText: 2024 Fredrik Ahlberg, Angus Gratton,
 # Espressif Systems (Shanghai) CO LTD, other contributors as noted.
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 from typing import Dict
 
 from .esp32c6 import ESP32C6ROM
+from ..loader import ESPLoader
 from ..util import FatalError
 
 
@@ -18,6 +19,7 @@ class ESP32H2ROM(ESP32C6ROM):
 
     DR_REG_LP_WDT_BASE = 0x600B1C00
     RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0  # LP_WDT_RWDT_CONFIG0_REG
+    RTC_CNTL_WDTCONFIG1_REG = DR_REG_LP_WDT_BASE + 0x0004  # LP_WDT_RWDT_CONFIG1_REG
     RTC_CNTL_WDTWPROTECT_REG = DR_REG_LP_WDT_BASE + 0x001C  # LP_WDT_RWDT_WPROTECT_REG
 
     RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x0020  # LP_WDT_SWD_CONFIG_REG
@@ -77,6 +79,9 @@ def get_crystal_freq(self):
         # ESP32H2 XTAL is fixed to 32MHz
         return 32
 
+    def hard_reset(self):
+        ESPLoader.hard_reset(self)
+
     def check_spi_connection(self, spi_connection):
         if not set(spi_connection).issubset(set(range(0, 28))):
             raise FatalError("SPI Pin numbers must be in the range 0-27.")
diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2023 Fredrik Ahlberg, Angus Gratton,
+# SPDX-FileCopyrightText: 2024 Fredrik Ahlberg, Angus Gratton,
 # Espressif Systems (Shanghai) CO LTD, other contributors as noted.
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
@@ -72,6 +72,10 @@ class ESP32P4ROM(ESP32ROM):
 
     FLASH_ENCRYPTED_WRITE_ALIGN = 16
 
+    UARTDEV_BUF_NO = 0x4FF3FEC8  # Variable in ROM .bss which indicates the port in use
+    UARTDEV_BUF_NO_USB_OTG = 5  # The above var when USB-OTG is used
+    UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6  # The above var when USB-JTAG/Serial is used
+
     MEMORY_MAP = [
         [0x00000000, 0x00010000, "PADDING"],
         [0x40000000, 0x4C000000, "DROM"],
@@ -105,6 +109,17 @@ class ESP32P4ROM(ESP32ROM):
         12: "KM_INIT_KEY",
     }
 
+    DR_REG_LP_WDT_BASE = 0x50116000
+    RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0  # LP_WDT_CONFIG0_REG
+    RTC_CNTL_WDTCONFIG1_REG = DR_REG_LP_WDT_BASE + 0x0004  # LP_WDT_CONFIG1_REG
+    RTC_CNTL_WDTWPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0018  # LP_WDT_WPROTECT_REG
+    RTC_CNTL_WDT_WKEY = 0x50D83AA1
+
+    RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x001C  # RTC_WDT_SWD_CONFIG_REG
+    RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18
+    RTC_CNTL_SWD_WPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0020  # RTC_WDT_SWD_WPROTECT_REG
+    RTC_CNTL_SWD_WKEY = 0x50D83AA1  # RTC_WDT_SWD_WKEY, same as WDT key in this case
+
     def get_pkg_version(self):
         num_word = 2
         return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 20) & 0x07
@@ -191,10 +206,42 @@ def change_baud(self, baud):
         ESPLoader.change_baud(self, baud)
 
     def _post_connect(self):
-        pass
-        # TODO: Disable watchdogs when USB modes are supported in the stub
-        # if not self.sync_stub_detected:  # Don't run if stub is reused
-        #     self.disable_watchdogs()
+        if not self.sync_stub_detected:  # Don't run if stub is reused
+            self.disable_watchdogs()
+
+    def uses_usb_otg(self):
+        """
+        Check the UARTDEV_BUF_NO register to see if USB-OTG console is being used
+        """
+        if self.secure_download_mode:
+            return False  # can't detect native USB in secure download mode
+        return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_OTG
+
+    def uses_usb_jtag_serial(self):
+        """
+        Check the UARTDEV_BUF_NO register to see if USB-JTAG/Serial is being used
+        """
+        if self.secure_download_mode:
+            return False  # can't detect USB-JTAG/Serial in secure download mode
+        return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_JTAG_SERIAL
+
+    def disable_watchdogs(self):
+        # When USB-JTAG/Serial is used, the RTC WDT and SWD watchdog are not reset
+        # and can then reset the board during flashing. Disable them.
+        if self.uses_usb_jtag_serial():
+            # Disable RTC WDT
+            self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_SWD_WKEY)
+            self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)
+            self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)
+
+            # Automatically feed SWD
+            self.write_reg(self.RTC_CNTL_SWD_WPROTECT_REG, self.RTC_CNTL_SWD_WKEY)
+            self.write_reg(
+                self.RTC_CNTL_SWD_CONF_REG,
+                self.read_reg(self.RTC_CNTL_SWD_CONF_REG)
+                | self.RTC_CNTL_SWD_AUTO_FEED_EN,
+            )
+            self.write_reg(self.RTC_CNTL_SWD_WPROTECT_REG, 0)
 
     def check_spi_connection(self, spi_connection):
         if not set(spi_connection).issubset(set(range(0, 55))):
@@ -205,6 +252,21 @@ def check_spi_connection(self, spi_connection):
                 "consider using other pins for SPI flash connection."
             )
 
+    def rtc_wdt_reset(self):
+        print("Hard resetting with RTC WDT...")
+        self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
+        self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000)  # set WDT timeout
+        self.write_reg(
+            self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
+        )  # enable WDT
+        self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)  # lock
+
+    def hard_reset(self):
+        if self.uses_usb_jtag_serial():
+            self.rtc_wdt_reset()
+        else:
+            ESPLoader.hard_reset(self)
+
 
 class ESP32P4StubLoader(ESP32P4ROM):
     """Access class for ESP32P4 stub loader, runs on top of ROM.
diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py
diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py
diff --git a/test/test_esptool.py b/test/test_esptool.py

Original file line number	Diff line number	Diff line change
`@@ -21,6 +21,7 @@`
`21`	`21`	`"reset_delay",`
`22`	`22`	`"open_port_attempts",`
`23`	`23`	`"custom_reset_sequence",`
	`24`	`+ "custom_hard_reset_sequence",`
`24`	`25`	`]`
`25`	`26`
`26`	`27`