pioarduino changes

Author: Jason2866

.github/workflows/dangerjs.yml

@@ -8,10 +8,10 @@ on:
 jobs:
   release_zips:
     name: Create release zip file
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-latest
     steps:
-      - name: Create a recursive clone source zip
-        uses: espressif/github-actions/release_zips@master
+      - name: Create a recursive clone source and stripped zip
+        uses: Jason2866/github-actions/release_zips@release_idf
         env:
             RELEASE_PROJECT_NAME: ESP-IDF
             GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

.github/workflows/docker.yml

@@ -35,7 +35,8 @@ if(CONFIG_ETH_ENABLED)
                          "src/phy/esp_eth_phy_ip101.c"
                          "src/phy/esp_eth_phy_ksz80xx.c"
                          "src/phy/esp_eth_phy_lan87xx.c"
-                         "src/phy/esp_eth_phy_rtl8201.c")
+                         "src/phy/esp_eth_phy_rtl8201.c"
+                         "src/phy/esp_eth_phy_jl1101.c")
     endif()
 
     if(CONFIG_ETH_SPI_ETHERNET_DM9051)

.github/workflows/release_zips.yml

@@ -374,6 +374,17 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config);
 */
 esp_eth_phy_t *esp_eth_phy_new_ksz80xx(const eth_phy_config_t *config);
 
+/**
+* @brief Create a PHY instance of JL1101
+*
+* @param[in] config: configuration of PHY
+*
+* @return
+*      - instance: create PHY instance successfully
+*      - NULL: create PHY instance failed because some error occurred
+*/
+esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config);
+
 #if CONFIG_ETH_SPI_ETHERNET_DM9051
 /**
 * @brief Create a PHY instance of DM9051

components/esp_eth/CMakeLists.txt

@@ -0,0 +1,186 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdlib.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_eth_phy_802_3.h"
+
+static const char *TAG = "jl1101";
+
+/***************Vendor Specific Register***************/
+
+/**
+ * @brief PSMR(Power Saving Mode Register)
+ *
+ */
+typedef union {
+    struct {
+        uint16_t reserved : 15;   /* Reserved */
+        uint16_t en_pwr_save : 1; /* Enable power saving mode */
+    };
+    uint16_t val;
+} psmr_reg_t;
+
+/**
+ * @brief PSR(Page Select Register)
+ *
+ */
+typedef union {
+    struct {
+        uint16_t page_select : 8; /* Select register page, default is 0 */
+        uint16_t reserved : 8;    /* Reserved */
+    };
+    uint16_t val;
+} psr_reg_t;
+#define ETH_PHY_PSR_REG_ADDR (0x1F)
+
+typedef struct {
+    phy_802_3_t phy_802_3;
+} phy_jl1101_t;
+
+static esp_err_t jl1101_page_select(phy_jl1101_t *jl1101, uint32_t page)
+{
+    esp_err_t ret = ESP_OK;
+    esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
+    psr_reg_t psr = {
+        .page_select = page
+    };
+    ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, jl1101->phy_802_3.addr, ETH_PHY_PSR_REG_ADDR, psr.val), err, TAG, "write PSR failed");
+    return ESP_OK;
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_update_link_duplex_speed(phy_jl1101_t *jl1101)
+{
+    esp_err_t ret = ESP_OK;
+    esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
+    uint32_t addr = jl1101->phy_802_3.addr;
+    eth_speed_t speed = ETH_SPEED_10M;
+    eth_duplex_t duplex = ETH_DUPLEX_HALF;
+    bmcr_reg_t bmcr;
+    bmsr_reg_t bmsr;
+    uint32_t peer_pause_ability = false;
+    anlpar_reg_t anlpar;
+    ESP_GOTO_ON_ERROR(jl1101_page_select(jl1101, 0), err, TAG, "select page 0 failed");
+    ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
+    ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
+    eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
+    /* check if link status changed */
+    if (jl1101->phy_802_3.link_status != link) {
+        /* when link up, read negotiation result */
+        if (link == ETH_LINK_UP) {
+            ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
+            if (bmcr.speed_select) {
+                speed = ETH_SPEED_100M;
+            } else {
+                speed = ETH_SPEED_10M;
+            }
+            if (bmcr.duplex_mode) {
+                duplex = ETH_DUPLEX_FULL;
+            } else {
+                duplex = ETH_DUPLEX_HALF;
+            }
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
+            /* if we're in duplex mode, and peer has the flow control ability */
+            if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
+                peer_pause_ability = 1;
+            } else {
+                peer_pause_ability = 0;
+            }
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
+        }
+        ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
+        jl1101->phy_802_3.link_status = link;
+    }
+    return ESP_OK;
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_get_link(esp_eth_phy_t *phy)
+{
+    esp_err_t ret = ESP_OK;
+    phy_jl1101_t *jl1101 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_jl1101_t, phy_802_3);
+    /* Updata information about link, speed, duplex */
+    ESP_GOTO_ON_ERROR(jl1101_update_link_duplex_speed(jl1101), err, TAG, "update link duplex speed failed");
+    return ESP_OK;
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
+{
+    esp_err_t ret = ESP_OK;
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+    esp_eth_mediator_t *eth = phy_802_3->eth;
+    if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
+        bmcr_reg_t bmcr;
+        ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
+        ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
+    }
+    return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_loopback(esp_eth_phy_t *phy, bool enable)
+{
+    esp_err_t ret = ESP_OK;
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+    bool auto_nego_en;
+    ESP_GOTO_ON_ERROR(jl1101_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
+    ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
+    return esp_eth_phy_802_3_loopback(phy_802_3, enable);
+err:
+    return ret;
+}
+
+static esp_err_t jl1101_init(esp_eth_phy_t *phy)
+{
+    esp_err_t ret = ESP_OK;
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+
+    /* Basic PHY init */
+    ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
+
+    /* Check PHY ID */
+    uint32_t oui;
+    uint8_t model;
+    ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
+    ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
+    ESP_GOTO_ON_FALSE(oui == 0x24DF10 && model == 0x2, ESP_FAIL, err, TAG, "wrong chip ID");
+
+    return ESP_OK;
+err:
+    return ret;
+}
+
+esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config)
+{
+    esp_eth_phy_t *ret = NULL;
+    phy_jl1101_t *jl1101 = calloc(1, sizeof(phy_jl1101_t));
+    ESP_GOTO_ON_FALSE(jl1101, NULL, err, TAG, "calloc jl1101 failed");
+    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&jl1101->phy_802_3, config) == ESP_OK,
+                        NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
+
+    // redefine functions which need to be customized for sake of jl1101
+    jl1101->phy_802_3.parent.init = jl1101_init;
+    jl1101->phy_802_3.parent.get_link = jl1101_get_link;
+    jl1101->phy_802_3.parent.autonego_ctrl = jl1101_autonego_ctrl;
+    jl1101->phy_802_3.parent.loopback = jl1101_loopback;
+
+    return &jl1101->phy_802_3.parent;
+err:
+    if (jl1101 != NULL) {
+        free(jl1101);
+    }
+    return ret;
+}

components/esp_eth/include/esp_eth_phy.h

@@ -287,6 +287,8 @@ static esp_err_t get_efuse_factory_mac(uint8_t *mac)
         uint32_t mac_low = ((uint32_t)mac[2] << 24) | ((uint32_t)mac[3] << 16) | ((uint32_t)mac[4] << 8) | mac[5];
         if (((mac_high & 0xFFFF) == 0x18fe) && (mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
             return ESP_OK;
+        } else if (esp_efuse_get_pkg_ver() ==  3) {
+            return ESP_OK;  // override for Xiaomi SOC's and maybe others too
         } else {
             ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
 #ifdef CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR

components/esp_eth/src/phy/esp_eth_phy_jl1101.c

@@ -905,7 +905,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void)   //psram init
         psram_io.psram_cs_io  = D0WDR2_V3_PSRAM_CS_IO;
     } else {
         ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %" PRIu32, pkg_ver);
-        abort();
+        return ESP_FAIL;
     }
     s_psram_cs_io = psram_io.psram_cs_io;
 

components/esp_hw_support/mac_addr.c

@@ -29,7 +29,7 @@
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{

components/esp_psram/esp32/esp_psram_impl_quad.c

@@ -23,7 +23,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                       // only one I2S on C3
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000)))    // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{