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Release pioarduino v5.5.0
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.github/workflows/dangerjs.yml

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.github/workflows/docker.yml

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.github/workflows/release_zips.yml

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Original file line numberDiff line numberDiff line change
@@ -8,11 +8,10 @@ on:
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jobs:
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release_zips:
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name: Create release zip file
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runs-on: ubuntu-24.04
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runs-on: ubuntu-latest
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steps:
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- name: Create a recursive clone source zip
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uses: espressif/release-zips-action@v1
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with:
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github_token: ${{ secrets.GITHUB_TOKEN }}
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release_project_name: ESP-IDF
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git_extra_args: --shallow-since="1 year ago"
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- name: Create a recursive clone source and stripped zip
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uses: Jason2866/github-actions/release_zips@release_idf
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env:
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RELEASE_PROJECT_NAME: ESP-IDF
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GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

components/esp_eth/CMakeLists.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,8 @@ if(CONFIG_ETH_ENABLED)
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"src/phy/esp_eth_phy_ip101.c"
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"src/phy/esp_eth_phy_ksz80xx.c"
3737
"src/phy/esp_eth_phy_lan87xx.c"
38-
"src/phy/esp_eth_phy_rtl8201.c")
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"src/phy/esp_eth_phy_rtl8201.c"
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"src/phy/esp_eth_phy_jl1101.c")
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endif()
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if(CONFIG_ETH_SPI_ETHERNET_DM9051)

components/esp_eth/include/esp_eth_phy.h

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Original file line numberDiff line numberDiff line change
@@ -374,6 +374,17 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config);
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*/
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esp_eth_phy_t *esp_eth_phy_new_ksz80xx(const eth_phy_config_t *config);
376376

377+
/**
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* @brief Create a PHY instance of JL1101
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*
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* @param[in] config: configuration of PHY
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*
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* @return
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* - instance: create PHY instance successfully
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* - NULL: create PHY instance failed because some error occurred
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*/
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esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config);
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377388
#if CONFIG_ETH_SPI_ETHERNET_DM9051
378389
/**
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* @brief Create a PHY instance of DM9051
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@@ -0,0 +1,186 @@
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/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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7+
#include <string.h>
8+
#include <stdlib.h>
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#include <sys/cdefs.h>
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#include "esp_log.h"
11+
#include "esp_check.h"
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#include "esp_eth_phy_802_3.h"
13+
14+
static const char *TAG = "jl1101";
15+
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/***************Vendor Specific Register***************/
17+
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/**
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* @brief PSMR(Power Saving Mode Register)
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*
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*/
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typedef union {
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struct {
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uint16_t reserved : 15; /* Reserved */
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uint16_t en_pwr_save : 1; /* Enable power saving mode */
26+
};
27+
uint16_t val;
28+
} psmr_reg_t;
29+
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/**
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* @brief PSR(Page Select Register)
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*
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*/
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typedef union {
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struct {
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uint16_t page_select : 8; /* Select register page, default is 0 */
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uint16_t reserved : 8; /* Reserved */
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};
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uint16_t val;
40+
} psr_reg_t;
41+
#define ETH_PHY_PSR_REG_ADDR (0x1F)
42+
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typedef struct {
44+
phy_802_3_t phy_802_3;
45+
} phy_jl1101_t;
46+
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static esp_err_t jl1101_page_select(phy_jl1101_t *jl1101, uint32_t page)
48+
{
49+
esp_err_t ret = ESP_OK;
50+
esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
51+
psr_reg_t psr = {
52+
.page_select = page
53+
};
54+
ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, jl1101->phy_802_3.addr, ETH_PHY_PSR_REG_ADDR, psr.val), err, TAG, "write PSR failed");
55+
return ESP_OK;
56+
err:
57+
return ret;
58+
}
59+
60+
static esp_err_t jl1101_update_link_duplex_speed(phy_jl1101_t *jl1101)
61+
{
62+
esp_err_t ret = ESP_OK;
63+
esp_eth_mediator_t *eth = jl1101->phy_802_3.eth;
64+
uint32_t addr = jl1101->phy_802_3.addr;
65+
eth_speed_t speed = ETH_SPEED_10M;
66+
eth_duplex_t duplex = ETH_DUPLEX_HALF;
67+
bmcr_reg_t bmcr;
68+
bmsr_reg_t bmsr;
69+
uint32_t peer_pause_ability = false;
70+
anlpar_reg_t anlpar;
71+
ESP_GOTO_ON_ERROR(jl1101_page_select(jl1101, 0), err, TAG, "select page 0 failed");
72+
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
73+
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
74+
eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
75+
/* check if link status changed */
76+
if (jl1101->phy_802_3.link_status != link) {
77+
/* when link up, read negotiation result */
78+
if (link == ETH_LINK_UP) {
79+
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
80+
if (bmcr.speed_select) {
81+
speed = ETH_SPEED_100M;
82+
} else {
83+
speed = ETH_SPEED_10M;
84+
}
85+
if (bmcr.duplex_mode) {
86+
duplex = ETH_DUPLEX_FULL;
87+
} else {
88+
duplex = ETH_DUPLEX_HALF;
89+
}
90+
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
91+
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
92+
/* if we're in duplex mode, and peer has the flow control ability */
93+
if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
94+
peer_pause_ability = 1;
95+
} else {
96+
peer_pause_ability = 0;
97+
}
98+
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
99+
}
100+
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
101+
jl1101->phy_802_3.link_status = link;
102+
}
103+
return ESP_OK;
104+
err:
105+
return ret;
106+
}
107+
108+
static esp_err_t jl1101_get_link(esp_eth_phy_t *phy)
109+
{
110+
esp_err_t ret = ESP_OK;
111+
phy_jl1101_t *jl1101 = __containerof(esp_eth_phy_into_phy_802_3(phy), phy_jl1101_t, phy_802_3);
112+
/* Updata information about link, speed, duplex */
113+
ESP_GOTO_ON_ERROR(jl1101_update_link_duplex_speed(jl1101), err, TAG, "update link duplex speed failed");
114+
return ESP_OK;
115+
err:
116+
return ret;
117+
}
118+
119+
static esp_err_t jl1101_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
120+
{
121+
esp_err_t ret = ESP_OK;
122+
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
123+
esp_eth_mediator_t *eth = phy_802_3->eth;
124+
if (cmd == ESP_ETH_PHY_AUTONEGO_EN) {
125+
bmcr_reg_t bmcr;
126+
ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
127+
ESP_GOTO_ON_FALSE(bmcr.en_loopback == 0, ESP_ERR_INVALID_STATE, err, TAG, "Autonegotiation can't be enabled while in loopback operation");
128+
}
129+
return esp_eth_phy_802_3_autonego_ctrl(phy_802_3, cmd, autonego_en_stat);
130+
err:
131+
return ret;
132+
}
133+
134+
static esp_err_t jl1101_loopback(esp_eth_phy_t *phy, bool enable)
135+
{
136+
esp_err_t ret = ESP_OK;
137+
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
138+
bool auto_nego_en;
139+
ESP_GOTO_ON_ERROR(jl1101_autonego_ctrl(phy, ESP_ETH_PHY_AUTONEGO_G_STAT, &auto_nego_en), err, TAG, "get status of autonegotiation failed");
140+
ESP_GOTO_ON_FALSE(!(auto_nego_en && enable), ESP_ERR_INVALID_STATE, err, TAG, "Unable to set loopback while autonegotiation is enabled. Disable it to use loopback");
141+
return esp_eth_phy_802_3_loopback(phy_802_3, enable);
142+
err:
143+
return ret;
144+
}
145+
146+
static esp_err_t jl1101_init(esp_eth_phy_t *phy)
147+
{
148+
esp_err_t ret = ESP_OK;
149+
phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
150+
151+
/* Basic PHY init */
152+
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_basic_phy_init(phy_802_3), err, TAG, "failed to init PHY");
153+
154+
/* Check PHY ID */
155+
uint32_t oui;
156+
uint8_t model;
157+
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_oui(phy_802_3, &oui), err, TAG, "read OUI failed");
158+
ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_read_manufac_info(phy_802_3, &model, NULL), err, TAG, "read manufacturer's info failed");
159+
ESP_GOTO_ON_FALSE(oui == 0x24DF10 && model == 0x2, ESP_FAIL, err, TAG, "wrong chip ID");
160+
161+
return ESP_OK;
162+
err:
163+
return ret;
164+
}
165+
166+
esp_eth_phy_t *esp_eth_phy_new_jl1101(const eth_phy_config_t *config)
167+
{
168+
esp_eth_phy_t *ret = NULL;
169+
phy_jl1101_t *jl1101 = calloc(1, sizeof(phy_jl1101_t));
170+
ESP_GOTO_ON_FALSE(jl1101, NULL, err, TAG, "calloc jl1101 failed");
171+
ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&jl1101->phy_802_3, config) == ESP_OK,
172+
NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
173+
174+
// redefine functions which need to be customized for sake of jl1101
175+
jl1101->phy_802_3.parent.init = jl1101_init;
176+
jl1101->phy_802_3.parent.get_link = jl1101_get_link;
177+
jl1101->phy_802_3.parent.autonego_ctrl = jl1101_autonego_ctrl;
178+
jl1101->phy_802_3.parent.loopback = jl1101_loopback;
179+
180+
return &jl1101->phy_802_3.parent;
181+
err:
182+
if (jl1101 != NULL) {
183+
free(jl1101);
184+
}
185+
return ret;
186+
}

components/esp_hw_support/mac_addr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -287,6 +287,8 @@ static esp_err_t get_efuse_factory_mac(uint8_t *mac)
287287
uint32_t mac_low = ((uint32_t)mac[2] << 24) | ((uint32_t)mac[3] << 16) | ((uint32_t)mac[4] << 8) | mac[5];
288288
if (((mac_high & 0xFFFF) == 0x18fe) && (mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
289289
return ESP_OK;
290+
} else if (esp_efuse_get_pkg_ver() == 3) {
291+
return ESP_OK; // override for Xiaomi SOC's and maybe others too
290292
} else {
291293
ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
292294
#ifdef CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR

components/esp_psram/esp32/esp_psram_impl_quad.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -905,7 +905,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
905905
psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
906906
} else {
907907
ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %" PRIu32, pkg_ver);
908-
abort();
908+
return ESP_FAIL;
909909
}
910910
s_psram_cs_io = psram_io.psram_cs_io;
911911

components/soc/esp32c2/include/soc/soc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
3030
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
3131
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
32-
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
32+
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI
3333
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
3434

3535
//Registers Operation {{

components/soc/esp32c3/include/soc/soc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3
2424
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
2525
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
26-
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
26+
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (DR_REG_SPI0_BASE - ((i) * 0x1000))) // only one GPSPI
2727
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
2828

2929
//Registers Operation {{

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