@@ -412,7 +412,7 @@ uint32_t ACAN2517FD::begin (const ACAN2517FDSettings & inSettings,
412412 // Bit 0: RTXAT ---> 1: Enable CiFIFOCONm.TXAT to control retransmission attempts
413413 data8 = 0x01 ; // Enable RTXAT to limit retransmissions (Flole)
414414 data8 |= mUsesTXQ ? (1 << 4 ) : 0x00 ; // Bug fix in 1.1.4 (thanks to danielhenz)
415- writeRegister8 (CON_REGISTER + 2 , data8); // DS20005688B, page 24
415+ writeRegister8 (CON_REGISTER + 2 , data8) ; // DS20005688B, page 24
416416 // ----------------------------------- Configure RX FIFO (FIFOCON, DS20005688B, page 52)
417417 data8 = inSettings.mControllerReceiveFIFOSize - 1 ; // Set receive FIFO size
418418 data8 |= inSettings.mControllerReceiveFIFOPayload << 5 ; // Payload
@@ -430,6 +430,7 @@ uint32_t ACAN2517FD::begin (const ACAN2517FDSettings & inSettings,
430430 data8 |= inSettings.mControllerTransmitFIFOPayload << 5 ; // Payload
431431 writeRegister8 (FIFOCON_REGISTER (TRANSMIT_FIFO_INDEX) + 3 , data8) ;
432432 data8 = 1 << 7 ; // FIFO is a Tx FIFO
433+ data8 |= 1 << 4 ; // TXATIE ---> 1: Enable Transmit Attempts Exhausted Interrupt
433434 writeRegister8 (FIFOCON_REGISTER (TRANSMIT_FIFO_INDEX), data8) ;
434435 mTransmitFIFOPayload = ACAN2517FDSettings::objectSizeForPayload (inSettings.mControllerTransmitFIFOPayload ) ;
435436 // ----------------------------------- Configure receive filters
@@ -450,6 +451,8 @@ uint32_t ACAN2517FD::begin (const ACAN2517FDSettings & inSettings,
450451 data8 = (1 << 1 ) ; // Receive FIFO Interrupt Enable
451452 data8 |= (1 << 0 ) ; // Transmit FIFO Interrupt Enable
452453 writeRegister8 (INT_REGISTER + 2 , data8) ;
454+ data8 = (1 << 2 ) ; // TXATIE ---> 1: Transmit Attempt Interrupt Enable bit
455+ writeRegister8 (INT_REGISTER + 3 , data8) ;
453456 // ----------------------------------- Program nominal bit rate (NBTCFG register)
454457 // bits 31-24: BRP - 1
455458 // bits 23-16: TSEG1 - 1
@@ -484,7 +487,7 @@ uint32_t ACAN2517FD::begin (const ACAN2517FDSettings & inSettings,
484487 data |= inSettings.mDataSJW - 1 ;
485488 writeRegister32 (DBTCFG_REGISTER, data) ;
486489 }
487- // ----------------------------------- Request mode (CON_REGISTER + 3)
490+ // ----------------------------------- Request mode (CON_REGISTER + 3, DS20005688B, page 24 )
488491 // bits 7-4: Transmit Bandwith Sharing Bits ---> 0
489492 // bit 3: Abort All Pending Transmissions bit --> 0
490493 mTXBWS_RequestedMode = inSettings.mRequestedMode | (TXBWS << 4 ) ;
@@ -571,6 +574,7 @@ bool ACAN2517FD::enterInTransmitBuffer (const CANFDMessage & inMessage) {
571574 if ((status & 1 ) == 0 ) { // FIFO is full
572575 uint8_t data8 = 1 << 7 ; // FIFO is a transmit FIFO
573576 data8 |= 1 ; // Enable "FIFO not full" interrupt
577+ data8 |= 1 << 4 ; // TXATIE ---> 1: Enable Transmit Attempts Exhausted Interrupt
574578 writeRegister8Assume_SPI_transaction (FIFOCON_REGISTER (TRANSMIT_FIFO_INDEX), data8) ;
575579 mHardwareTxFIFOFull = true ;
576580 }
@@ -650,59 +654,69 @@ void ACAN2517FD::appendInControllerTxFIFO (const CANFDMessage & inMessage) {
650654// ----------------------------------------------------------------------------------------------------------------------
651655
652656bool ACAN2517FD::sendViaTXQ (const CANFDMessage & inMessage) {
653- // --- Enter message only if TXQ FIFO is not full (see DS20005688B, page 50)
654- const bool TXQNotFull = mUsesTXQ && (readRegister8Assume_SPI_transaction (TXQSTA_REGISTER) & 1 ) != 0 ;
655- if (TXQNotFull) {
656- const uint16_t ramAddress = (uint16_t ) (0x400 + readRegister32Assume_SPI_transaction (TXQUA_REGISTER)) ;
657- // --- Write identifier: if an extended frame is sent, identifier bits sould be reordered (see DS20005678B, page 27)
658- uint32_t idf = inMessage.id ;
659- if (inMessage.ext ) {
660- idf = ((inMessage.id >> 18 ) & 0x7FF ) | ((inMessage.id & 0x3FFFF ) << 11 ) ;
661- }
662- // --- Write DLC field, FDF, BRS, RTR, IDE bits
663- uint32_t flags = lengthCodeForLength (inMessage.len ) ;
664- if (inMessage.ext ) {
665- flags |= 1 << 4 ; // Set EXT bit
657+ bool ok = mUsesTXQ ;
658+ if (ok) {
659+ uint8_t sta = readRegister8Assume_SPI_transaction (TXQSTA_REGISTER) ;
660+ // --- Check Transmit Attempts Exhausted Interrupt Pending bit
661+ ok = (sta & (1 << 4 )) != 0 ;
662+ if (ok) {
663+ writeRegister8Assume_SPI_transaction (TXQSTA_REGISTER, ~ (1 << 4 )) ;
664+ }else {
665+ // --- Enter message only if TXQ FIFO is not full (see DS20005688B, page 50)
666+ ok = (sta & 1 ) != 0 ;
666667 }
667- switch (inMessage.type ) {
668- case CANFDMessage::CAN_REMOTE :
669- flags |= 1 << 5 ; // Set RTR bit
670- break ;
671- case CANFDMessage::CAN_DATA :
672- break ;
673- case CANFDMessage::CANFD_NO_BIT_RATE_SWITCH :
674- flags |= 1 << 7 ; // Set FDF bit
675- break ;
676- case CANFDMessage::CANFD_WITH_BIT_RATE_SWITCH :
677- flags |= 1 << 7 ; // Set FDF bit
678- if (mHasDataBitRate ) {
679- flags |= 1 << 6 ; // Set BRS bit
668+ if (ok) {
669+ const uint16_t ramAddress = (uint16_t ) (0x400 + readRegister32Assume_SPI_transaction (TXQUA_REGISTER)) ;
670+ // --- Write identifier: if an extended frame is sent, identifier bits sould be reordered (see DS20005678B, page 27)
671+ uint32_t idf = inMessage.id ;
672+ if (inMessage.ext ) {
673+ idf = ((inMessage.id >> 18 ) & 0x7FF ) | ((inMessage.id & 0x3FFFF ) << 11 ) ;
680674 }
681- break ;
682- }
683- // --- Word count
684- const uint32_t wordCount = (inMessage.len + 3 ) / 4 ;
685- // --- Transfer frame to the MCP2517FD
686- uint8_t buff[74 ] = {0 } ;
687- // --- Enter command
688- const uint16_t writeCommand = (ramAddress & 0x0FFF ) | (0b0010 << 12 ) ;
689- buff[0 ] = writeCommand >> 8 ;
690- buff[1 ] = writeCommand & 0xFF ;
691- // --- Enter values
692- enterU32InBufferAtIndex (idf, buff, 2 ) ;
693- enterU32InBufferAtIndex (flags, buff, 6 ) ;
694- for (uint32_t i=0 ; i < wordCount ; i++) {
695- enterU32InBufferAtIndex (inMessage.data32 [i], buff, 10 + 4 * i) ;
675+ // --- Write DLC field, FDF, BRS, RTR, IDE bits
676+ uint32_t flags = lengthCodeForLength (inMessage.len ) ;
677+ if (inMessage.ext ) {
678+ flags |= 1 << 4 ; // Set EXT bit
679+ }
680+ switch (inMessage.type ) {
681+ case CANFDMessage::CAN_REMOTE :
682+ flags |= 1 << 5 ; // Set RTR bit
683+ break ;
684+ case CANFDMessage::CAN_DATA :
685+ break ;
686+ case CANFDMessage::CANFD_NO_BIT_RATE_SWITCH :
687+ flags |= 1 << 7 ; // Set FDF bit
688+ break ;
689+ case CANFDMessage::CANFD_WITH_BIT_RATE_SWITCH :
690+ flags |= 1 << 7 ; // Set FDF bit
691+ if (mHasDataBitRate ) {
692+ flags |= 1 << 6 ; // Set BRS bit
693+ }
694+ break ;
695+ }
696+ // --- Word count
697+ const uint32_t wordCount = (inMessage.len + 3 ) / 4 ;
698+ // --- Transfer frame to the MCP2517FD
699+ uint8_t buff[74 ] = {0 } ;
700+ // --- Enter command
701+ const uint16_t writeCommand = (ramAddress & 0x0FFF ) | (0b0010 << 12 ) ;
702+ buff[0 ] = writeCommand >> 8 ;
703+ buff[1 ] = writeCommand & 0xFF ;
704+ // --- Enter values
705+ enterU32InBufferAtIndex (idf, buff, 2 ) ;
706+ enterU32InBufferAtIndex (flags, buff, 6 ) ;
707+ for (uint32_t i=0 ; i < wordCount ; i++) {
708+ enterU32InBufferAtIndex (inMessage.data32 [i], buff, 10 + 4 * i) ;
709+ }
710+ // --- SPI transfer
711+ assertCS () ;
712+ mSPI .transfer (buff, 10 + 4 * wordCount) ;
713+ deassertCS () ;
714+ // --- Increment FIFO, send message (see DS20005688B, page 48)
715+ const uint8_t data8 = (1 << 0 ) | (1 << 1 ) ; // Set UINC bit, TXREQ bit
716+ writeRegister8Assume_SPI_transaction (TXQCON_REGISTER + 1 , data8);
696717 }
697- // --- SPI transfer
698- assertCS () ;
699- mSPI .transfer (buff, 10 + 4 * wordCount) ;
700- deassertCS () ;
701- // --- Increment FIFO, send message (see DS20005688B, page 48)
702- const uint8_t data8 = (1 << 0 ) | (1 << 1 ) ; // Set UINC bit, TXREQ bit
703- writeRegister8Assume_SPI_transaction (TXQCON_REGISTER + 1 , data8);
704718 }
705- return TXQNotFull ;
719+ return ok ;
706720}
707721
708722// ----------------------------------------------------------------------------------------------------------------------
@@ -825,7 +839,12 @@ bool ACAN2517FD::isr_core (void) {
825839 receiveInterrupt () ;
826840 handled = true ;
827841 }
828- if ((it & (1 << 0 )) != 0 ) { // Transmit FIFO interrupt
842+ if ((it & (1 << 10 )) != 0 ) { // Transmit Attempt interrupt
843+ // --- Clear Pending Transmit Attempt interrupt bit
844+ writeRegister8Assume_SPI_transaction (FIFOSTA_REGISTER (TRANSMIT_FIFO_INDEX), ~ (1 << 4 )) ;
845+ transmitInterrupt () ;
846+ handled = true ;
847+ }else if ((it & (1 << 0 )) != 0 ) { // Transmit FIFO interrupt
829848 transmitInterrupt () ;
830849 handled = true ;
831850 }
@@ -863,7 +882,8 @@ void ACAN2517FD::transmitInterrupt (void) { // Generated if hardware transmit FI
863882 if (hasMessage) {
864883 appendInControllerTxFIFO (message) ;
865884 }else { // No message in transmit FIFO: disable "FIFO not full" interrupt
866- const uint8_t data8 = 1 << 7 ; // FIFO is a transmit FIFO
885+ uint8_t data8 = 1 << 7 ; // FIFO is a transmit FIFO
886+ data8 |= 1 << 4 ; // TXATIE ---> 1: Enable Transmit Attempts Exhausted Interrupt
867887 writeRegister8Assume_SPI_transaction (FIFOCON_REGISTER (TRANSMIT_FIFO_INDEX), data8) ;
868888 mHardwareTxFIFOFull = false ;
869889 }
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