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Ivan KlokovFabiano Rosas
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tests/qtest: QTest example for RISC-V CSR register
Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
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tests/qtest/meson.build

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@@ -274,7 +274,7 @@ qtests_s390x = \
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qtests_riscv32 = \
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(config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : [])
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qtests_riscv64 = \
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qtests_riscv64 = ['riscv-csr-test'] + \
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(unpack_edk2_blobs ? ['bios-tables-test'] : [])
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qos_test_ss = ss.source_set()

tests/qtest/riscv-csr-test.c

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/*
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* QTest testcase for RISC-V CSRs
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*
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* Copyright (c) 2024 Syntacore.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#define CSR_MVENDORID 0xf11
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#define CSR_MISELECT 0x350
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static void run_test_csr(void)
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{
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uint64_t res;
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uint64_t val = 0;
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QTestState *qts = qtest_init("-machine virt -cpu veyron-v1");
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res = qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val);
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g_assert_cmpint(res, ==, 0);
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g_assert_cmpint(val, ==, 0x61f);
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val = 0xff;
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res = qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val);
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g_assert_cmpint(res, ==, 0);
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val = 0;
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res = qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val);
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g_assert_cmpint(res, ==, 0);
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g_assert_cmpint(val, ==, 0xff);
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qtest_quit(qts);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/cpu/csr", run_test_csr);
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return g_test_run();
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}

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