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Merge tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu into staging
Qtest pull request - RISCV CSR test - migration recover changed to OOB - removal of dead code in test-x86-cpuid-compat # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmeKbx4QHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnRD7D/9v4ovvGn/IwSXjjpOpkjhCSgV8TMi1F61P # hqB5TTCY8yejvT7JauplMUHmcJsVCNx+HF36D+YjxBjqrhQE8vzPRXgcLxHL9RX4 # Kwgdk24kFKADE3gsiys9gOpwRhmtY0/2CT5LvitfJRMxUNPtm0Mr7qM3Z0Taeusu # lxZgIMTBeNakpY5vua8nlLQ4r+/Df6S3TFFAaQ4UYab/T5zHVcjKaySXDlT1QXpp # M+Be21jPxuUYJnKCSxMCUtuY9wkSPcITzJW91V+JxL9STSpsKpnQe10JWDRbwLBt # /am2Jg5f8iFEblCwr5aQRMwXB+e/Y7K4qKPOUalj+weGnCXh9DmWPXnV6qzdZNO8 # sePKoFj1AMtqbVf3iOpDBRkH8dECiDh1jHmflW1grF0BuOwOw8dKYW+i2qz9ZDiW # rKWKfRcZZ059aOCQWqpMC9TGQ8osMC/v6GGJwiPBDLapGjnAm5d1683w4Z1l8tAg # vf9yti2mpzK15PB6doEj/IuZr8WKWFMklizmMMZpXgHIUpjtm3JFKXX/jGHcD3KU # E8F4ns3zPMlq7ncIwc6GADRB3XzEuzzuXAaEO8HMN0fYHevfnFIon749udyBDI/n # a1/CTzTmchItwzgpdvcoiKO6gkg6DO9n08QULCMPSVCtl5KAlz5yuwxWGI/rM6u7 # ixPi8i24oA== # =i4AD # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Jan 2025 09:54:22 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'qtest-20250117-pull-request' of https://gitlab.com/farosas/qemu: tests/qtest/test-x86-cpuid-compat: Remove tests related to pc-i440fx-2.3 tests/qtest/migration: Use out-of-band execution for migrate-recover tests/qtest: Introduce qtest_init_with_env_and_capabilities() tests/qtest: QTest example for RISC-V CSR register target/riscv: Add RISC-V CSR qtest support Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2 parents 0e3aff9 + aa601bd commit 20fac49

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9 files changed

+210
-24
lines changed

9 files changed

+210
-24
lines changed

hw/riscv/riscv_hart.c

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@
2222
#include "qapi/error.h"
2323
#include "qemu/module.h"
2424
#include "system/reset.h"
25+
#include "system/qtest.h"
26+
#include "qemu/cutils.h"
2527
#include "hw/sysbus.h"
2628
#include "target/riscv/cpu.h"
2729
#include "hw/qdev-properties.h"
@@ -41,6 +43,55 @@ static void riscv_harts_cpu_reset(void *opaque)
4143
cpu_reset(CPU(cpu));
4244
}
4345

46+
#ifndef CONFIG_USER_ONLY
47+
static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
48+
{
49+
RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
50+
CPURISCVState *env = &cpu->env;
51+
52+
int ret = RISCV_EXCP_NONE;
53+
if (strcmp(cmd, "get_csr") == 0) {
54+
ret = riscv_csrr(env, csrno, (target_ulong *)val);
55+
} else if (strcmp(cmd, "set_csr") == 0) {
56+
ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
57+
MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
58+
}
59+
60+
g_assert(ret == RISCV_EXCP_NONE);
61+
}
62+
63+
static bool csr_qtest_callback(CharBackend *chr, gchar **words)
64+
{
65+
if (strcmp(words[0], "csr") == 0) {
66+
67+
uint64_t cpu;
68+
uint64_t val;
69+
int rc, csr;
70+
71+
rc = qemu_strtou64(words[2], NULL, 0, &cpu);
72+
g_assert(rc == 0);
73+
rc = qemu_strtoi(words[3], NULL, 0, &csr);
74+
g_assert(rc == 0);
75+
rc = qemu_strtou64(words[4], NULL, 0, &val);
76+
g_assert(rc == 0);
77+
csr_call(words[1], cpu, csr, &val);
78+
79+
qtest_send_prefix(chr);
80+
qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
81+
82+
return true;
83+
}
84+
85+
return false;
86+
}
87+
88+
static void riscv_cpu_register_csr_qtest_callback(void)
89+
{
90+
static GOnce once;
91+
g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback);
92+
}
93+
#endif
94+
4495
static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
4596
char *cpu_type, Error **errp)
4697
{
@@ -58,6 +109,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp)
58109

59110
s->harts = g_new0(RISCVCPU, s->num_harts);
60111

112+
#ifndef CONFIG_USER_ONLY
113+
riscv_cpu_register_csr_qtest_callback();
114+
#endif
115+
61116
for (n = 0; n < s->num_harts; n++) {
62117
if (!riscv_hart_realize(s, n, s->cpu_type, errp)) {
63118
return;

tests/qtest/libqtest.c

Lines changed: 43 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -543,19 +543,33 @@ QTestState *qtest_init_without_qmp_handshake(const char *extra_args)
543543
return qtest_init_internal(qtest_qemu_binary(NULL), extra_args);
544544
}
545545

546-
QTestState *qtest_init_with_env(const char *var, const char *extra_args)
546+
QTestState *qtest_init_with_env_and_capabilities(const char *var,
547+
const char *extra_args,
548+
QList *capabilities)
547549
{
548550
QTestState *s = qtest_init_internal(qtest_qemu_binary(var), extra_args);
549551
QDict *greeting;
550552

551553
/* Read the QMP greeting and then do the handshake */
552554
greeting = qtest_qmp_receive(s);
553555
qobject_unref(greeting);
554-
qobject_unref(qtest_qmp(s, "{ 'execute': 'qmp_capabilities' }"));
556+
if (capabilities) {
557+
qtest_qmp_assert_success(s,
558+
"{ 'execute': 'qmp_capabilities', "
559+
"'arguments': { 'enable': %p } }",
560+
qobject_ref(capabilities));
561+
} else {
562+
qtest_qmp_assert_success(s, "{ 'execute': 'qmp_capabilities' }");
563+
}
555564

556565
return s;
557566
}
558567

568+
QTestState *qtest_init_with_env(const char *var, const char *extra_args)
569+
{
570+
return qtest_init_with_env_and_capabilities(var, extra_args, NULL);
571+
}
572+
559573
QTestState *qtest_init(const char *extra_args)
560574
{
561575
return qtest_init_with_env(NULL, extra_args);
@@ -1218,6 +1232,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name,
12181232
return 0;
12191233
}
12201234

1235+
static void qtest_rsp_csr(QTestState *s, uint64_t *val)
1236+
{
1237+
gchar **args;
1238+
uint64_t ret;
1239+
int rc;
1240+
1241+
args = qtest_rsp_args(s, 3);
1242+
1243+
rc = qemu_strtou64(args[1], NULL, 16, &ret);
1244+
g_assert(rc == 0);
1245+
rc = qemu_strtou64(args[2], NULL, 16, val);
1246+
g_assert(rc == 0);
1247+
1248+
g_strfreev(args);
1249+
}
1250+
1251+
uint64_t qtest_csr_call(QTestState *s, const char *name,
1252+
uint64_t cpu, int csr,
1253+
uint64_t *val)
1254+
{
1255+
qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n",
1256+
name, cpu, csr, *val);
1257+
1258+
qtest_rsp_csr(s, val);
1259+
return 0;
1260+
}
1261+
12211262
void qtest_add_func(const char *str, void (*fn)(void))
12221263
{
12231264
gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str);

tests/qtest/libqtest.h

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919

2020
#include "qapi/qmp/qobject.h"
2121
#include "qapi/qmp/qdict.h"
22+
#include "qapi/qmp/qlist.h"
2223
#include "libqmp.h"
2324

2425
typedef struct QTestState QTestState;
@@ -68,6 +69,22 @@ QTestState *qtest_init(const char *extra_args);
6869
*/
6970
QTestState *qtest_init_with_env(const char *var, const char *extra_args);
7071

72+
/**
73+
* qtest_init_with_env_and_capabilities:
74+
* @var: Environment variable from where to take the QEMU binary
75+
* @extra_args: Other arguments to pass to QEMU. CAUTION: these
76+
* arguments are subject to word splitting and shell evaluation.
77+
* @capabilities: list of QMP capabilities (strings) to enable
78+
*
79+
* Like qtest_init_with_env(), but enable specified capabilities during
80+
* hadshake.
81+
*
82+
* Returns: #QTestState instance.
83+
*/
84+
QTestState *qtest_init_with_env_and_capabilities(const char *var,
85+
const char *extra_args,
86+
QList *capabilities);
87+
7188
/**
7289
* qtest_init_without_qmp_handshake:
7390
* @extra_args: other arguments to pass to QEMU. CAUTION: these
@@ -600,6 +617,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name,
600617
uint32_t nargs, uint64_t args,
601618
uint32_t nret, uint64_t ret);
602619

620+
/**
621+
* qtest_csr_call:
622+
* @s: #QTestState instance to operate on.
623+
* @name: name of the command to call.
624+
* @cpu: hart number.
625+
* @csr: CSR number.
626+
* @val: Value for reading/writing.
627+
*
628+
* Call an RISC-V CSR read/write function
629+
*/
630+
uint64_t qtest_csr_call(QTestState *s, const char *name,
631+
uint64_t cpu, int csr,
632+
uint64_t *val);
633+
603634
/**
604635
* qtest_bufread:
605636
* @s: #QTestState instance to operate on.

tests/qtest/meson.build

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,7 @@ qtests_s390x = \
274274
qtests_riscv32 = \
275275
(config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : [])
276276

277-
qtests_riscv64 = \
277+
qtests_riscv64 = ['riscv-csr-test'] + \
278278
(unpack_edk2_blobs ? ['bios-tables-test'] : [])
279279

280280
qos_test_ss = ss.source_set()

tests/qtest/migration/framework.c

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,16 @@ static void cleanup(const char *filename)
194194
unlink(path);
195195
}
196196

197+
static QList *migrate_start_get_qmp_capabilities(const MigrateStart *args)
198+
{
199+
QList *capabilities = qlist_new();
200+
201+
if (args->oob) {
202+
qlist_append_str(capabilities, "oob");
203+
}
204+
return capabilities;
205+
}
206+
197207
int migrate_start(QTestState **from, QTestState **to, const char *uri,
198208
MigrateStart *args)
199209
{
@@ -210,6 +220,7 @@ int migrate_start(QTestState **from, QTestState **to, const char *uri,
210220
const char *machine_alias, *machine_opts = "";
211221
g_autofree char *machine = NULL;
212222
const char *bootpath;
223+
g_autoptr(QList) capabilities = migrate_start_get_qmp_capabilities(args);
213224

214225
if (args->use_shmem) {
215226
if (!g_file_test("/dev/shm", G_FILE_TEST_IS_DIR)) {
@@ -314,7 +325,8 @@ int migrate_start(QTestState **from, QTestState **to, const char *uri,
314325
args->opts_source ? args->opts_source : "",
315326
ignore_stderr);
316327
if (!args->only_target) {
317-
*from = qtest_init_with_env(QEMU_ENV_SRC, cmd_source);
328+
*from = qtest_init_with_env_and_capabilities(QEMU_ENV_SRC, cmd_source,
329+
capabilities);
318330
qtest_qmp_set_event_callback(*from,
319331
migrate_watch_for_events,
320332
&src_state);
@@ -334,7 +346,8 @@ int migrate_start(QTestState **from, QTestState **to, const char *uri,
334346
shmem_opts ? shmem_opts : "",
335347
args->opts_target ? args->opts_target : "",
336348
ignore_stderr);
337-
*to = qtest_init_with_env(QEMU_ENV_DST, cmd_target);
349+
*to = qtest_init_with_env_and_capabilities(QEMU_ENV_DST, cmd_target,
350+
capabilities);
338351
qtest_qmp_set_event_callback(*to,
339352
migrate_watch_for_events,
340353
&dst_state);
@@ -601,6 +614,12 @@ void test_postcopy_recovery_common(MigrateCommon *args)
601614
QTestState *from, *to;
602615
g_autofree char *uri = NULL;
603616

617+
/*
618+
* Always enable OOB QMP capability for recovery tests, migrate-recover is
619+
* executed out-of-band
620+
*/
621+
args->start.oob = true;
622+
604623
/* Always hide errors for postcopy recover tests since they're expected */
605624
args->start.hide_stderr = true;
606625

tests/qtest/migration/framework.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,8 @@ typedef struct {
109109
const char *opts_target;
110110
/* suspend the src before migrating to dest. */
111111
bool suspend_me;
112+
/* enable OOB QMP capability */
113+
bool oob;
112114
} MigrateStart;
113115

114116
typedef enum PostcopyRecoveryFailStage {

tests/qtest/migration/migration-qmp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -464,7 +464,7 @@ void migrate_continue(QTestState *who, const char *state)
464464
void migrate_recover(QTestState *who, const char *uri)
465465
{
466466
qtest_qmp_assert_success(who,
467-
"{ 'execute': 'migrate-recover', "
467+
"{ 'exec-oob': 'migrate-recover', "
468468
" 'id': 'recover-cmd', "
469469
" 'arguments': { 'uri': %s } }",
470470
uri);

tests/qtest/riscv-csr-test.c

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
/*
2+
* QTest testcase for RISC-V CSRs
3+
*
4+
* Copyright (c) 2024 Syntacore.
5+
*
6+
* This program is free software; you can redistribute it and/or modify it
7+
* under the terms of the GNU General Public License as published by the
8+
* Free Software Foundation; either version 2 of the License, or
9+
* (at your option) any later version.
10+
*
11+
* This program is distributed in the hope that it will be useful, but WITHOUT
12+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14+
* for more details.
15+
*/
16+
17+
#include "qemu/osdep.h"
18+
#include "libqtest.h"
19+
20+
#define CSR_MVENDORID 0xf11
21+
#define CSR_MISELECT 0x350
22+
23+
static void run_test_csr(void)
24+
{
25+
uint64_t res;
26+
uint64_t val = 0;
27+
28+
QTestState *qts = qtest_init("-machine virt -cpu veyron-v1");
29+
30+
res = qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val);
31+
32+
g_assert_cmpint(res, ==, 0);
33+
g_assert_cmpint(val, ==, 0x61f);
34+
35+
val = 0xff;
36+
res = qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val);
37+
38+
g_assert_cmpint(res, ==, 0);
39+
40+
val = 0;
41+
res = qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val);
42+
43+
g_assert_cmpint(res, ==, 0);
44+
g_assert_cmpint(val, ==, 0xff);
45+
46+
qtest_quit(qts);
47+
}
48+
49+
int main(int argc, char **argv)
50+
{
51+
g_test_init(&argc, &argv, NULL);
52+
53+
qtest_add_func("/cpu/csr", run_test_csr);
54+
55+
return g_test_run();
56+
}

tests/qtest/test-x86-cpuid-compat.c

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -357,19 +357,6 @@ int main(int argc, char **argv)
357357
"486", "xstore=on", "pc-i440fx-2.7",
358358
"xlevel2", 0);
359359
}
360-
/*
361-
* QEMU 2.3.0 had auto-level enabled for CPUID[7], already,
362-
* and the compat code that sets default level shouldn't
363-
* disable the auto-level=7 code:
364-
*/
365-
if (qtest_has_machine("pc-i440fx-2.3")) {
366-
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.3/off",
367-
"Penryn", NULL, "pc-i440fx-2.3",
368-
"level", 4);
369-
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.3/on",
370-
"Penryn", "erms=on", "pc-i440fx-2.3",
371-
"level", 7);
372-
}
373360
if (qtest_has_machine("pc-i440fx-2.9")) {
374361
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.9/off",
375362
"Conroe", NULL, "pc-i440fx-2.9",
@@ -384,11 +371,6 @@ int main(int argc, char **argv)
384371
* code on old machine-types. Just check that the compat code
385372
* is working correctly:
386373
*/
387-
if (qtest_has_machine("pc-i440fx-2.3")) {
388-
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.3",
389-
"SandyBridge", NULL, "pc-i440fx-2.3",
390-
"xlevel", 0x8000000a);
391-
}
392374
if (qtest_has_machine("pc-i440fx-2.4")) {
393375
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-off",
394376
"SandyBridge", NULL, "pc-i440fx-2.4",

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