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‎api/next/63796.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
pkg sync, method (*WaitGroup) Go(func()) #63769

‎doc/next/6-stdlib/99-minor/os/15388.md‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,14 @@
1-
On Windows, [NewFile] supports overlapped (a.k.a non-blocking) file handles even
2-
when the handle can't be added to the Go runtime I/O Completion Port (IOCP), normally
3-
because it is already attached to another IOCP. The I/O operations will be performed in
4-
a blocking manner instead of using the Go runtime IOCP.
5-
Particularly, this means that is now possible to reliably pass overlapped named pipes and
6-
sockets to a Go process standard input, output, and error.
1+
On Windows, [NewFile] now supports handles opened for asynchronous I/O (that is,
2+
[syscall.FILE_FLAG_OVERLAPPED] is specified in the [syscall.CreateFile] call).
3+
These handles are associated with the Go runtime's I/O completion port,
4+
which provides the following benefits for the resulting [File]:
5+
6+
- I/O methods ([File.Read], [File.Write], [File.ReadAt], and [File.WriteAt]) do not block an OS thread.
7+
- Deadline methods ([File.SetDeadline], [File.SetReadDeadline], and [File.SetWriteDeadline]) are supported.
8+
9+
This enhancement is especially beneficial for applications that communicate via named pipes on Windows.
10+
11+
Note that a handle can only be associated with one completion port at a time.
12+
If the handle provided to [NewFile] is already associated with a completion port,
13+
the returned [File] is downgraded to synchronous I/O mode.
14+
In this case, I/O methods will block an OS thread, and the deadline methods have no effect.

‎doc/next/6-stdlib/99-minor/sync/63769.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
[WaitGroup] has added a new method [WaitGroup.Go],
2+
that makes the common pattern of creating and counting goroutines more convenient.

‎src/cmd/compile/internal/arm64/ssa.go‎

Lines changed: 4 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -147,13 +147,13 @@ func genIndexedOperand(op ssa.Op, base, idx int16) obj.Addr {
147147
// Reg: base register, Index: (shifted) index register
148148
mop := obj.Addr{Type: obj.TYPE_MEM, Reg: base}
149149
switch op {
150-
case ssa.OpARM64MOVDloadidx8, ssa.OpARM64MOVDstoreidx8, ssa.OpARM64MOVDstorezeroidx8,
150+
case ssa.OpARM64MOVDloadidx8, ssa.OpARM64MOVDstoreidx8,
151151
ssa.OpARM64FMOVDloadidx8, ssa.OpARM64FMOVDstoreidx8:
152152
mop.Index = arm64.REG_LSL | 3<<5 | idx&31
153-
case ssa.OpARM64MOVWloadidx4, ssa.OpARM64MOVWUloadidx4, ssa.OpARM64MOVWstoreidx4, ssa.OpARM64MOVWstorezeroidx4,
153+
case ssa.OpARM64MOVWloadidx4, ssa.OpARM64MOVWUloadidx4, ssa.OpARM64MOVWstoreidx4,
154154
ssa.OpARM64FMOVSloadidx4, ssa.OpARM64FMOVSstoreidx4:
155155
mop.Index = arm64.REG_LSL | 2<<5 | idx&31
156-
case ssa.OpARM64MOVHloadidx2, ssa.OpARM64MOVHUloadidx2, ssa.OpARM64MOVHstoreidx2, ssa.OpARM64MOVHstorezeroidx2:
156+
case ssa.OpARM64MOVHloadidx2, ssa.OpARM64MOVHUloadidx2, ssa.OpARM64MOVHstoreidx2:
157157
mop.Index = arm64.REG_LSL | 1<<5 | idx&31
158158
default: // not shifted
159159
mop.Index = idx
@@ -188,7 +188,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
188188
p.From.Reg = x
189189
p.To.Type = obj.TYPE_REG
190190
p.To.Reg = y
191-
case ssa.OpARM64MOVDnop:
191+
case ssa.OpARM64MOVDnop, ssa.OpARM64ZERO:
192192
// nothing to do
193193
case ssa.OpLoadReg:
194194
if v.Type.IsFlags() {
@@ -591,35 +591,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
591591
p.To.Type = obj.TYPE_MEM
592592
p.To.Reg = v.Args[0].Reg()
593593
ssagen.AddAux(&p.To, v)
594-
case ssa.OpARM64MOVBstorezero,
595-
ssa.OpARM64MOVHstorezero,
596-
ssa.OpARM64MOVWstorezero,
597-
ssa.OpARM64MOVDstorezero:
598-
p := s.Prog(v.Op.Asm())
599-
p.From.Type = obj.TYPE_REG
600-
p.From.Reg = arm64.REGZERO
601-
p.To.Type = obj.TYPE_MEM
602-
p.To.Reg = v.Args[0].Reg()
603-
ssagen.AddAux(&p.To, v)
604-
case ssa.OpARM64MOVBstorezeroidx,
605-
ssa.OpARM64MOVHstorezeroidx,
606-
ssa.OpARM64MOVWstorezeroidx,
607-
ssa.OpARM64MOVDstorezeroidx,
608-
ssa.OpARM64MOVHstorezeroidx2,
609-
ssa.OpARM64MOVWstorezeroidx4,
610-
ssa.OpARM64MOVDstorezeroidx8:
611-
p := s.Prog(v.Op.Asm())
612-
p.To = genIndexedOperand(v.Op, v.Args[0].Reg(), v.Args[1].Reg())
613-
p.From.Type = obj.TYPE_REG
614-
p.From.Reg = arm64.REGZERO
615-
case ssa.OpARM64MOVQstorezero:
616-
p := s.Prog(v.Op.Asm())
617-
p.From.Type = obj.TYPE_REGREG
618-
p.From.Reg = arm64.REGZERO
619-
p.From.Offset = int64(arm64.REGZERO)
620-
p.To.Type = obj.TYPE_MEM
621-
p.To.Reg = v.Args[0].Reg()
622-
ssagen.AddAux(&p.To, v)
623594
case ssa.OpARM64BFI,
624595
ssa.OpARM64BFXIL:
625596
p := s.Prog(v.Op.Asm())

‎src/cmd/compile/internal/escape/utils.go‎

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -227,10 +227,29 @@ func HeapAllocReason(n ir.Node) string {
227227
}
228228
}
229229

230+
elem := n.Type().Elem()
231+
if elem.Size() == 0 {
232+
// TODO: stack allocate these? See #65685.
233+
return "zero-sized element"
234+
}
230235
if !ir.IsSmallIntConst(*r) {
231-
return "non-constant size"
236+
// For non-constant sizes, we do a hybrid approach:
237+
//
238+
// if cap <= K {
239+
// var backing [K]E
240+
// s = backing[:len:cap]
241+
// } else {
242+
// s = makeslice(E, len, cap)
243+
// }
244+
//
245+
// It costs a constant amount of stack space, but may
246+
// avoid a heap allocation.
247+
// Note we have to be careful that assigning s[i] = v
248+
// still escapes v, because we forbid heap->stack pointers.
249+
// Implementation is in ../walk/builtin.go:walkMakeSlice.
250+
return ""
232251
}
233-
if t := n.Type(); t.Elem().Size() != 0 && ir.Int64Val(*r) > ir.MaxImplicitStackVarSize/t.Elem().Size() {
252+
if ir.Int64Val(*r) > ir.MaxImplicitStackVarSize/elem.Size() {
234253
return "too large for stack"
235254
}
236255
}

‎src/cmd/compile/internal/ir/symtab.go‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ type symsStruct struct {
3030
Goschedguarded *obj.LSym
3131
Growslice *obj.LSym
3232
InterfaceSwitch *obj.LSym
33+
MallocGC *obj.LSym
3334
Memmove *obj.LSym
3435
Msanread *obj.LSym
3536
Msanwrite *obj.LSym

‎src/cmd/compile/internal/ssa/_gen/ARM64.rules‎

Lines changed: 0 additions & 111 deletions
Original file line numberDiff line numberDiff line change
@@ -485,9 +485,6 @@
485485
(STP [16] dst (Select0 <typ.UInt64> (LDP [16] src mem)) (Select1 <typ.UInt64> (LDP [16] src mem))
486486
(STP dst (Select0 <typ.UInt64> (LDP src mem)) (Select1 <typ.UInt64> (LDP src mem)) mem))))
487487

488-
(MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i+8] ptr mem)) && x.Uses == 1 && setPos(v, x.Pos) && clobber(x) => (MOVQstorezero {s} [i] ptr mem)
489-
(MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i-8] ptr mem)) && x.Uses == 1 && setPos(v, x.Pos) && clobber(x) => (MOVQstorezero {s} [i-8] ptr mem)
490-
491488
// strip off fractional word move
492489
(Move [s] dst src mem) && s%16 != 0 && s%16 <= 8 && s > 16 =>
493490
(Move [8]
@@ -817,21 +814,6 @@
817814
(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
818815
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
819816
(FMOVDstore [off1+int32(off2)] {sym} ptr val mem)
820-
(MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
821-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
822-
(MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
823-
(MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
824-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
825-
(MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
826-
(MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
827-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
828-
(MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
829-
(MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
830-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
831-
(MOVDstorezero [off1+int32(off2)] {sym} ptr mem)
832-
(MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
833-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
834-
(MOVQstorezero [off1+int32(off2)] {sym} ptr mem)
835817

836818
// register indexed store
837819
(MOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem)
@@ -947,70 +929,6 @@
947929
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
948930
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
949931
(FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
950-
(MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
951-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
952-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
953-
(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
954-
(MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
955-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
956-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
957-
(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
958-
(MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
959-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
960-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
961-
(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
962-
(MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
963-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
964-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
965-
(MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
966-
(MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
967-
&& canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
968-
&& (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
969-
(MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
970-
971-
// store zero
972-
(MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
973-
(MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
974-
(MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
975-
(MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVDstorezero [off] {sym} ptr mem)
976-
(STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem) => (MOVQstorezero [off] {sym} ptr mem)
977-
978-
// register indexed store zero
979-
(MOVDstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVDstorezeroidx ptr idx mem)
980-
(MOVWstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWstorezeroidx ptr idx mem)
981-
(MOVHstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHstorezeroidx ptr idx mem)
982-
(MOVBstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBstorezeroidx ptr idx mem)
983-
(MOVDstoreidx ptr idx (MOVDconst [0]) mem) => (MOVDstorezeroidx ptr idx mem)
984-
(MOVWstoreidx ptr idx (MOVDconst [0]) mem) => (MOVWstorezeroidx ptr idx mem)
985-
(MOVHstoreidx ptr idx (MOVDconst [0]) mem) => (MOVHstorezeroidx ptr idx mem)
986-
(MOVBstoreidx ptr idx (MOVDconst [0]) mem) => (MOVBstorezeroidx ptr idx mem)
987-
(MOVDstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVDstorezero [int32(c)] ptr mem)
988-
(MOVDstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVDstorezero [int32(c)] idx mem)
989-
(MOVWstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVWstorezero [int32(c)] ptr mem)
990-
(MOVWstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVWstorezero [int32(c)] idx mem)
991-
(MOVHstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHstorezero [int32(c)] ptr mem)
992-
(MOVHstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVHstorezero [int32(c)] idx mem)
993-
(MOVBstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVBstorezero [int32(c)] ptr mem)
994-
(MOVBstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVBstorezero [int32(c)] idx mem)
995-
996-
// shifted register indexed store zero
997-
(MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (MOVDstorezeroidx8 ptr idx mem)
998-
(MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWstorezeroidx4 ptr idx mem)
999-
(MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHstorezeroidx2 ptr idx mem)
1000-
(MOVDstorezeroidx ptr (SLLconst [3] idx) mem) => (MOVDstorezeroidx8 ptr idx mem)
1001-
(MOVWstorezeroidx ptr (SLLconst [2] idx) mem) => (MOVWstorezeroidx4 ptr idx mem)
1002-
(MOVHstorezeroidx ptr (SLLconst [1] idx) mem) => (MOVHstorezeroidx2 ptr idx mem)
1003-
(MOVHstorezeroidx ptr (ADD idx idx) mem) => (MOVHstorezeroidx2 ptr idx mem)
1004-
(MOVDstorezeroidx (SLLconst [3] idx) ptr mem) => (MOVDstorezeroidx8 ptr idx mem)
1005-
(MOVWstorezeroidx (SLLconst [2] idx) ptr mem) => (MOVWstorezeroidx4 ptr idx mem)
1006-
(MOVHstorezeroidx (SLLconst [1] idx) ptr mem) => (MOVHstorezeroidx2 ptr idx mem)
1007-
(MOVHstorezeroidx (ADD idx idx) ptr mem) => (MOVHstorezeroidx2 ptr idx mem)
1008-
(MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) => (MOVDstorezeroidx8 ptr idx mem)
1009-
(MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) => (MOVWstorezeroidx4 ptr idx mem)
1010-
(MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) => (MOVHstorezeroidx2 ptr idx mem)
1011-
(MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (MOVDstorezero [int32(c<<3)] ptr mem)
1012-
(MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (MOVWstorezero [int32(c<<2)] ptr mem)
1013-
(MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) && is32Bit(c<<1) => (MOVHstorezero [int32(c<<1)] ptr mem)
1014932

1015933
// replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
1016934
// these seem to have bad interaction with other rules, resulting in slower code
@@ -1025,35 +943,6 @@
1025943
//(FMOVDload [off] {sym} ptr (FMOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
1026944
//(LDP [off] {sym} ptr (STP [off2] {sym2} ptr2 x y _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x y
1027945

1028-
(MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1029-
(MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1030-
(MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1031-
(MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1032-
(MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1033-
(MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1034-
(MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0])
1035-
1036-
(MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _))
1037-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1038-
(MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _))
1039-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1040-
(MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _))
1041-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1042-
(MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _))
1043-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1044-
(MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _))
1045-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1046-
(MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _))
1047-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1048-
(MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _))
1049-
&& (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0])
1050-
1051-
(MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0])
1052-
(MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0])
1053-
(MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0])
1054-
(MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0])
1055-
(MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0])
1056-
1057946
// don't extend before store
1058947
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
1059948
(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)

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