From 23d795305a7bfb74b4bbc4f44b75a56653884547 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Mon, 25 Nov 2024 10:43:45 +0500 Subject: [PATCH 1/6] Removing code to handle CLK_BUFs at output side of fabric --- design_edit/src/rs_design_edit.cc | 142 ------------------------------ 1 file changed, 142 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index cb0509b14..00b739e1d 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -1126,80 +1126,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - bool is_clk_out(Module *mod, Wire* rhs_wire, std::unordered_set &prims) - { - bool is_clk_output = false; - for (auto cell : mod->cells()) { - string module_name = remove_backslashes(cell->type.str()); - if (std::find(prims.begin(), prims.end(), module_name) != - prims.end()) { - for (auto conn : cell->connections()) { - IdString portName = conn.first; - RTLIL::SigSpec actual = conn.second; - if (actual.is_chunk()) { - const RTLIL::SigChunk chunk = actual.as_chunk(); - if(chunk.wire == NULL) continue; - if(chunk.wire->name.str() == rhs_wire->name.str() && - (module_name.substr(0, 4) == "CLK_")) - { - is_clk_output = true; - } - } - } - } - } - return is_clk_output; - } - - void update_prim_connections(Module* mod, std::unordered_set &prims, std::unordered_set &del_intermediate_wires) - { - for (auto cell : mod->cells()) { - string module_name = remove_backslashes(cell->type.str()); - if (std::find(prims.begin(), prims.end(), module_name) != - prims.end()) { - for (auto conn : cell->connections()) { - IdString portName = conn.first; - RTLIL::SigSpec actual = conn.second; - if (actual.is_chunk()) { - const RTLIL::SigChunk chunk = actual.as_chunk(); - RTLIL::Wire *wire = actual.as_chunk().wire; - if(chunk.wire == NULL) continue; - for (const auto& connection : connections_to_remove) - { - const Yosys::RTLIL::SigSpec lhs = connection.first; - const Yosys::RTLIL::SigSpec rhs = connection.second; - const RTLIL::SigChunk lhs_chunk = lhs.as_chunk(); - const RTLIL::SigChunk rhs_chunk = rhs.as_chunk(); - if ((chunk.width == chunk.wire->width && chunk.offset == 0) && - (lhs_chunk.width == lhs_chunk.wire->width && lhs_chunk.offset == 0) && - (lhs_chunk.wire->name.str() == chunk.wire->name.str())) - { - cell->unsetPort(portName); - cell->setPort(portName, rhs); - del_intermediate_wires.insert(wire); - } else if ((chunk.width == 1) && - (lhs_chunk.wire->name.str() == chunk.wire->name.str())) - { - if (lhs_chunk.width == 1) - { - cell->unsetPort(portName); - cell->setPort(portName, rhs); - del_intermediate_wires.insert(wire); - } else if (lhs_chunk.width == lhs_chunk.wire->width && lhs_chunk.offset == 0) { - unsigned offset = chunk.offset + chunk.wire->start_offset ; - auto conn_rhs = connection.second.to_sigbit_vector(); - cell->unsetPort(portName); - cell->setPort(portName, conn_rhs.at(offset)); - del_intermediate_wires.insert(wire); - } - } - } - } - } - } - } - } - void clean_flattened(Module *mod) { for(auto &conn : mod->connections()) @@ -1730,41 +1656,6 @@ struct DesignEditRapidSilicon : public ScriptPass { end = high_resolution_clock::now(); elapsed_time (start, end); - start = high_resolution_clock::now(); - log("Handling I_BUF->Fabric->CLK_BUF\n"); - for (auto &conn : original_mod->connections()) { - RTLIL::SigSpec lhs = conn.first; - RTLIL::SigSpec rhs = conn.second; - if(lhs.is_chunk() && rhs.is_chunk()) - { - const RTLIL::SigChunk lhs_chunk = lhs.as_chunk(); - const RTLIL::SigChunk rhs_chunk = rhs.as_chunk(); - if((lhs_chunk.wire != nullptr) && (rhs_chunk.wire != nullptr)) - { - if((lhs_chunk.wire->port_input || lhs_chunk.wire->port_output) && - (rhs_chunk.wire->port_input || rhs_chunk.wire->port_output) && - (outputs.find(lhs_chunk.wire->name.str()) == outputs.end())) - { - if(is_clk_out(original_mod, rhs_chunk.wire, primitives) && - inputs.find(rhs_chunk.wire->name.str()) == inputs.end()) - { - lhs_chunk.wire->port_input = false; - lhs_chunk.wire->port_output = false; - rhs_chunk.wire->port_input = false; - rhs_chunk.wire->port_output = false; - connections_to_remove.insert(conn); - } - } - } - } - } - - remove_extra_conns(original_mod); - connections_to_remove.clear(); - update_prim_connections(original_mod, primitives, orig_intermediate_wires); - end = high_resolution_clock::now(); - elapsed_time (start, end); - for (const auto& prim_conn : io_prim_conn) { const std::vector& connected_wires = prim_conn.second; if(connected_wires.size() < 1) continue; @@ -1888,39 +1779,6 @@ struct DesignEditRapidSilicon : public ScriptPass { end = high_resolution_clock::now(); elapsed_time (start, end); - start = high_resolution_clock::now(); - log("Handling I_BUF->Fabric->CLK_BUF in interface module\n"); - for (auto &conn : interface_mod->connections()) { - RTLIL::SigSpec lhs = conn.first; - RTLIL::SigSpec rhs = conn.second; - if(lhs.is_chunk() && rhs.is_chunk()) - { - const RTLIL::SigChunk lhs_chunk = lhs.as_chunk(); - const RTLIL::SigChunk rhs_chunk = rhs.as_chunk(); - if((lhs_chunk.wire != nullptr) && (rhs_chunk.wire != nullptr)) - { - if((lhs_chunk.wire->port_input || lhs_chunk.wire->port_output) && - (rhs_chunk.wire->port_input || rhs_chunk.wire->port_output) && - (outputs.find(lhs_chunk.wire->name.str()) == outputs.end())) - { - if(is_clk_out(interface_mod, lhs_chunk.wire, primitives) && - inputs.find(rhs_chunk.wire->name.str()) == inputs.end()) - { - lhs_chunk.wire->port_input = false; - lhs_chunk.wire->port_output = false; - rhs_chunk.wire->port_input = false; - rhs_chunk.wire->port_output = false; - connections_to_remove.insert(conn); - } - } - } - } - } - - update_prim_connections(interface_mod, primitives, interface_intermediate_wires); - end = high_resolution_clock::now(); - elapsed_time (start, end); - interface_mod->connections_.clear(); connections_to_remove.clear(); start = high_resolution_clock::now(); From 22eb8488c617ff9bb62e28abe486ed49c86cbf04 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Tue, 26 Nov 2024 10:55:27 +0500 Subject: [PATCH 2/6] Removing flatten pass and merging wrapper and interface modules --- design_edit/src/rs_design_edit.cc | 112 ++++-------------------------- 1 file changed, 12 insertions(+), 100 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 00b739e1d..f059139fe 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -1610,10 +1610,7 @@ struct DesignEditRapidSilicon : public ScriptPass { intersection_copy_remove(new_ins, new_outs, interface_wires); intersect(interface_wires, keep_wires); } - - Module *interface_mod = _design->top_module()->clone(); - std::string interface_mod_name = "\\interface_" + original_mod_name; - interface_mod->name = interface_mod_name; + Module *wrapper_mod = original_mod->clone(); std::string wrapper_mod_name = "\\" + original_mod_name; wrapper_mod->name = wrapper_mod_name; @@ -1738,8 +1735,8 @@ struct DesignEditRapidSilicon : public ScriptPass { remove_io_fab_prim(original_mod); start = high_resolution_clock::now(); - log("Deleting non-primitive cells and upgrading wires to ports in interface module\n"); - for (auto cell : interface_mod->cells()) { + log("Deleting non-primitive cells\n"); + for (auto cell : wrapper_mod->cells()) { string module_name = remove_backslashes(cell->type.str()); if (std::find(primitives.begin(), primitives.end(), module_name) == primitives.end()) { @@ -1747,21 +1744,18 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - delete_cells(interface_mod, remove_non_prims); + delete_cells(wrapper_mod, remove_non_prims); - for (auto wire : interface_mod->wires()) { + for (auto wire : wrapper_mod->wires()) { std::string wire_name = wire->name.str(); if (new_ins.find(wire_name) != new_ins.end()) { - wire->port_output = true; continue; } if (new_outs.find(wire_name) != new_outs.end()) { - wire->port_input = true; continue; } if (common_clks_resets.find(wire_name) != common_clks_resets.end()) { - wire->port_output = true; continue; } if (interface_wires.find(wire_name) != interface_wires.end()) { @@ -1773,21 +1767,12 @@ struct DesignEditRapidSilicon : public ScriptPass { if (outputs.find(wire_name) != outputs.end()) { continue; } - del_interface_wires.insert(wire); } - end = high_resolution_clock::now(); elapsed_time (start, end); - interface_mod->connections_.clear(); + wrapper_mod->connections_.clear(); connections_to_remove.clear(); - start = high_resolution_clock::now(); - log("Removing extra wires from interface module\n"); - for (auto wire : del_interface_wires) { - interface_mod->remove({wire}); - } - end = high_resolution_clock::now(); - elapsed_time (start, end); delete_wires(original_mod, orig_intermediate_wires); fixup_mod_ports(original_mod); @@ -1801,28 +1786,10 @@ struct DesignEditRapidSilicon : public ScriptPass { rem_extra_wires(original_mod); reportInfoFabricClocks(original_mod); - - delete_wires(interface_mod, interface_intermediate_wires); - interface_mod->fixup_ports(); - } - - start = high_resolution_clock::now(); - log("Removing cells from wrapper module\n"); - for (auto cell : wrapper_mod->cells()) { - string module_name = cell->type.str(); - remove_wrapper_cells.push_back(cell); - } - - for (auto cell : remove_wrapper_cells) { - wrapper_mod->remove(cell); } - end = high_resolution_clock::now(); - elapsed_time (start, end); - - wrapper_mod->connections_.clear(); start = high_resolution_clock::now(); - log("Instantiating fabric and interface modules\n"); + log("Instantiating fabric module\n"); // Add instances of the original and interface modules to the wrapper module Cell *orig_mod_inst = wrapper_mod->addCell("\\fabric_instance", original_mod->name); for (auto wire : original_mod->wires()) { @@ -1833,57 +1800,18 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - for (auto wire : interface_mod->wires()) { + + for (auto wire : wrapper_mod->wires()) { RTLIL::SigSpec conn = wire; std::string wire_name = wire->name.str(); - if (wire->port_input || wire->port_output) { - interface_inst_conns.insert(wire_name); + if (orig_inst_conns.find(wire_name) != orig_inst_conns.end()) { + orig_mod_inst->setPort(wire_name, conn); } } - if (supported_tech) - { - Cell *interface_mod_inst = - wrapper_mod->addCell(NEW_ID, interface_mod->name); - for (auto wire : wrapper_mod->wires()) { - RTLIL::SigSpec conn = wire; - std::string wire_name = wire->name.str(); - if (orig_inst_conns.find(wire_name) == orig_inst_conns.end() && - interface_inst_conns.find(wire_name) == interface_inst_conns.end() && - interface_wires.find(wire_name) == interface_wires.end()) { - del_wrapper_wires.insert(wire); - } else { - if (orig_inst_conns.find(wire_name) != orig_inst_conns.end()) { - orig_mod_inst->setPort(wire_name, conn); - } - if (supported_tech) - { - if (interface_inst_conns.find(wire_name) != - interface_inst_conns.end()) { - interface_mod_inst->setPort(wire_name, conn); - } - } - } - } - } else { - for (auto wire : wrapper_mod->wires()) { - RTLIL::SigSpec conn = wire; - std::string wire_name = wire->name.str(); - if (orig_inst_conns.find(wire_name) == orig_inst_conns.end()) { - del_wrapper_wires.insert(wire); - } else { - orig_mod_inst->setPort(wire_name, conn); - } - } - } - end = high_resolution_clock::now(); - elapsed_time (start, end); - start = high_resolution_clock::now(); log("Removing extra wires from wrapper module\n"); - for (auto wire : del_wrapper_wires) { - wrapper_mod->remove({wire}); - } + //ToDo end = high_resolution_clock::now(); elapsed_time (start, end); @@ -1892,22 +1820,6 @@ struct DesignEditRapidSilicon : public ScriptPass { wrapper_mod->fixup_ports(); new_design->add(wrapper_mod); - if (supported_tech) - { - new_design->add(interface_mod); - } - end = high_resolution_clock::now(); - elapsed_time (start, end); - start = high_resolution_clock::now(); - log("Flattening wrapper module\n"); - Pass::call(new_design, "flatten"); - end = high_resolution_clock::now(); - elapsed_time (start, end); - handle_inout_connection(wrapper_mod); - - start = high_resolution_clock::now(); - log("Removing extra assigns from wrapper module\n"); - clean_flattened(wrapper_mod); end = high_resolution_clock::now(); elapsed_time (start, end); From 248c4c5e55b6925632e21cc320e51b3a4f00fad4 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 27 Nov 2024 16:18:41 +0500 Subject: [PATCH 3/6] Deleting extra wires from wrapper module --- design_edit/src/rs_design_edit.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index f059139fe..93a61d2f8 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -1811,7 +1811,7 @@ struct DesignEditRapidSilicon : public ScriptPass { start = high_resolution_clock::now(); log("Removing extra wires from wrapper module\n"); - //ToDo + rem_extra_wires(wrapper_mod); end = high_resolution_clock::now(); elapsed_time (start, end); From b740d3623339728c63f07c9d009eb3c7a281a262 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Thu, 28 Nov 2024 10:40:24 +0500 Subject: [PATCH 4/6] Code clean-up --- design_edit/src/rs_design_edit.cc | 124 +----------------------------- design_edit/src/rs_design_edit.h | 4 - 2 files changed, 1 insertion(+), 127 deletions(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 93a61d2f8..b6a4c9a8e 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -83,23 +83,16 @@ struct DesignEditRapidSilicon : public ScriptPass { std::vector remove_prims; std::vector remove_fab_prims; // TODO : change to unoredred set later std::vector remove_non_prims; - std::vector remove_wrapper_cells; std::unordered_set wires_interface; std::unordered_set del_ins; std::unordered_set del_outs; - std::unordered_set del_interface_wires; - std::unordered_set del_wrapper_wires; std::unordered_set del_unused; std::set> connections_to_remove; std::unordered_set orig_intermediate_wires; - std::unordered_set interface_intermediate_wires; - std::map wrapper_conns; std::map> io_prim_conn, intf_prim_conn; - std::map inout_conn_map; std::map ifab_sig_map; std::map> ofab_sig_map, ofab_conns; pool prim_out_bits; - pool unused_prim_outs; pool used_bits; pool orig_ins, orig_outs, fab_outs, fab_ins; @@ -888,57 +881,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - void handle_inout_connection(Module* mod) - { - for(auto &conn : mod->connections()) - { - std::vector conn_lhs = conn.first.to_sigbit_vector(); - std::vector conn_rhs = conn.second.to_sigbit_vector(); - bool remove_conn = false; - for (size_t i = 0; i < conn_lhs.size(); ++i) - { - if (conn_rhs[i].wire != nullptr) - if (conn_rhs[i].wire->port_input && conn_rhs[i].wire->port_output) - { - inout_conn_map[conn_lhs[i]] = conn_rhs[i]; - remove_conn = true; - } - } - if (remove_conn) - { - connections_to_remove.insert(conn); - } - } - - remove_extra_conns(mod); - connections_to_remove.clear(); - - for (auto cell : mod->cells()) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - bool unset_port = true; - RTLIL::SigSpec sigspec; - for (SigBit bit : conn.second) - { - if (inout_conn_map.count(bit) > 0) - { - if (unset_port) - { - cell->unsetPort(portName); - unset_port = false; - } - sigspec.append(inout_conn_map[bit]); - } else { - sigspec.append(bit); - } - } - if (!unset_port) cell->setPort(portName, sigspec); - } - } - } - void process_wire(Cell *cell, const IdString &portName, RTLIL::Wire *wire) { if (cell->input(portName)) { if (wire->port_input) { @@ -1126,71 +1068,7 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - void clean_flattened(Module *mod) - { - for(auto &conn : mod->connections()) - { - std::vector conn_lhs = conn.first.to_sigbit_vector(); - std::vector conn_rhs = conn.second.to_sigbit_vector(); - for (size_t i = 0; i < conn_lhs.size(); i++) { - if (conn_lhs[i].wire != nullptr && conn_rhs[i].wire != nullptr) - { - wrapper_conns.insert(std::make_pair(conn_lhs[i], conn_rhs[i])); - } else { - std::cerr << "Unexpected behaviour from flatten pass" << std::endl; - } - } - } - - for (auto cell : mod->cells()) { - string module_name = cell->type.str(); - bool is_fabric_instance = (module_name.substr(0, 8) == "\\fabric_") ? true : false; - if (is_fabric_instance) continue; - for (auto conn : cell->connections()) { - IdString portName = conn.first; - bool unset_port = true; - RTLIL::SigSpec sigspec; - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) - { - bool appended = false; - for (auto it = wrapper_conns.begin(); it != wrapper_conns.end(); ++it) { - if (it->second == bit) { - if (unset_port) { - cell->unsetPort(portName); - unset_port = false; - } - sigspec.append(it->first); - appended = true; - break; - } else if (it->first == bit) { - if (unset_port) { - cell->unsetPort(portName); - unset_port = false; - } - sigspec.append(it->second); - appended = true; - break; - } - } - if(!appended) sigspec.append(bit); - } - else { - sigspec.append(bit); - } - } - if (!unset_port) - { - cell->setPort(portName, sigspec); - } - } - } - - mod->connections_.clear(); - } - - void elapsed_time (time_point start, + void elapsed_time(time_point start, time_point end) { auto duration = duration_cast(end - start); diff --git a/design_edit/src/rs_design_edit.h b/design_edit/src/rs_design_edit.h index aafe6e132..f324a7338 100644 --- a/design_edit/src/rs_design_edit.h +++ b/design_edit/src/rs_design_edit.h @@ -62,7 +62,6 @@ enum Technologies { GENERIC, GENESIS, GENESIS_2, GENESIS_3 }; std::vector pins; std::vector wrapper_files; std::vector post_route_wrapper; -std::unordered_set clk_outs; std::unordered_set primitives; std::unordered_set out_prims; std::unordered_set soc_intf_prims; @@ -76,7 +75,6 @@ std::unordered_set in_prim_outs; std::unordered_set io_prim_wires; std::unordered_set common_clks_resets; std::unordered_set orig_inst_conns; -std::unordered_set interface_inst_conns; std::unordered_set keep_wires; std::string io_config_json; std::string sdc_file; @@ -85,7 +83,5 @@ std::string tech; std::vector tokenizeString(const std::string &input); void processSdcFile(std::istream &input); -void get_loc_map_by_io(); -void write_checker_file(); #endif // DESIGN_EDIT_UTILS_H \ No newline at end of file From 9ac25385b4e3ef976a422d2617b8d0e6b134181a Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Thu, 28 Nov 2024 11:52:12 +0000 Subject: [PATCH 5/6] Incremented patch version --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5ec54cf0d..4bcc53ae1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -17,7 +17,7 @@ set(VERSION_MINOR 0) -set(VERSION_PATCH 382) +set(VERSION_PATCH 383) From fc117f38bce4dc88f84857790a2049b6cd67e617 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Thu, 28 Nov 2024 17:00:50 +0500 Subject: [PATCH 6/6] Correcting typo --- design_edit/src/rs_design_edit.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index b6a4c9a8e..6f3ef7611 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -815,7 +815,7 @@ struct DesignEditRapidSilicon : public ScriptPass { string module_name = remove_backslashes(cell->type.str()); if (std::find(primitives.begin(), primitives.end(), module_name) != primitives.end()) { - //EDA-3010: output primitives cal also have danlging output wire + //EDA-3010: output primitives can also have danlging output wire //bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false; //if (is_out_prim) continue; // Upgrading dangling outs of input primtives to output ports