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Basic io vhdl models
Increment Version #306: Pull request #353 opened by alaindargelas
July 1, 2024 04:19 14s basic_io_vhdl_models
July 1, 2024 04:19 14s
Basic IOs VHDL sim models
Increment Version #305: Pull request #352 opened by alaindargelas
June 30, 2024 18:56 13s basic_io_vhdl_models
June 30, 2024 18:56 13s
Basic I/O primitives VHDL sim models
Increment Version #304: Pull request #351 opened by alaindargelas
June 30, 2024 18:37 16s basic_io_vhdl_models
June 30, 2024 18:37 16s
Release 1.4.0
Increment Version #303: Pull request #350 opened by alaindargelas
June 25, 2024 16:27 13s release_1_4_0
June 25, 2024 16:27 13s
cosmetic changes
Increment Version #300: Pull request #347 opened by awaisabbas006
June 14, 2024 06:16 14s SEC_RnD
June 14, 2024 06:16 14s
Release 1.3.8
Increment Version #299: Pull request #346 opened by alaindargelas
June 14, 2024 00:34 14s release_1_3_8
June 14, 2024 00:34 14s
fix known issues on obs_clean
Increment Version #298: Pull request #345 opened by BessonThierry
June 13, 2024 16:13 13s BessonThierry:main
June 13, 2024 16:13 13s
New SEC check Pass for stage wise equivalence checking
Increment Version #297: Pull request #344 opened by AYYAZmayo
June 13, 2024 11:28 20s SEC_RnD
June 13, 2024 11:28 20s
Sec rn d
Increment Version #296: Pull request #343 opened by AYYAZmayo
June 13, 2024 11:01 18s SEC_RnD
June 13, 2024 11:01 18s
terminate synthesis on illegla clk connection
Increment Version #295: Pull request #342 opened by awaisabbas006
June 13, 2024 10:50 14s main
June 13, 2024 10:50 14s
Thierry's opt clean
Increment Version #294: Pull request #340 opened by alaindargelas
June 12, 2024 22:20 13s clean_opt
June 12, 2024 22:20 13s
Release 1.3.7
Increment Version #293: Pull request #339 opened by alaindargelas
June 12, 2024 19:18 10m 18s sim_update_1_3_7
June 12, 2024 19:18 10m 18s
Revert "error on illegal use if clock signal: EDA-2953"
Increment Version #292: Pull request #338 opened by alaindargelas
June 12, 2024 19:03 2m 18s revert-333-main
June 12, 2024 19:03 2m 18s
Revert "introducing new cleanup for EDA-2859"
Increment Version #291: Pull request #337 opened by alaindargelas
June 12, 2024 19:02 59s revert-334-main
June 12, 2024 19:02 59s
Revert "Update release 1.3.7"
Increment Version #290: Pull request #336 opened by alaindargelas
June 12, 2024 18:54 1m 20s revert-335-sim_model_1_3_7
June 12, 2024 18:54 1m 20s
Update release 1.3.7
Increment Version #289: Pull request #335 opened by alaindargelas
June 12, 2024 17:58 4m 36s sim_model_1_3_7
June 12, 2024 17:58 4m 36s
introducing new cleanup for EDA-2859
Increment Version #288: Pull request #334 opened by BessonThierry
June 12, 2024 17:19 2m 7s BessonThierry:main
June 12, 2024 17:19 2m 7s
error on illegal use if clock signal: EDA-2953
Increment Version #287: Pull request #333 opened by awaisabbas006
June 12, 2024 11:15 19s main
June 12, 2024 11:15 19s
TDP_RAM18 fix, FCLK_BUF, PLL fix
Increment Version #286: Pull request #332 opened by alaindargelas
June 11, 2024 00:39 17s FCLK_BUF
June 11, 2024 00:39 17s
improve design editing
Increment Version #285: Pull request #331 opened by awaisabbas006
June 6, 2024 13:03 21s SEC_RnD
June 6, 2024 13:03 21s
Updated flow
Increment Version #284: Pull request #330 opened by awaisabbas006
June 4, 2024 06:57 14s main
June 4, 2024 06:57 14s
Adding new pass for SEC project
Increment Version #283: Pull request #329 opened by awaisabbas006
May 31, 2024 13:03 16s main
May 31, 2024 13:03 16s
sim model release 1.3.1
Increment Version #282: Pull request #328 opened by alaindargelas
May 31, 2024 00:47 13s sim_1.3.1
May 31, 2024 00:47 13s