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lines changed- VERSION.md+1-1
- docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst+3-3
- openfpga/src/base/openfpga_verilog_command_template.h+5-2
- openfpga/src/base/openfpga_verilog_template.h+14-9
- openfpga/src/fpga_verilog/fabric_verilog_options.cpp+60-4
- openfpga/src/fpga_verilog/fabric_verilog_options.h+30-3
- openfpga/src/fpga_verilog/verilog_grid.cpp+6-9
- openfpga/src/fpga_verilog/verilog_lut.cpp+4-4
- openfpga/src/fpga_verilog/verilog_memory.cpp+14-21
- openfpga/src/fpga_verilog/verilog_module_writer.cpp+21-13
- openfpga/src/fpga_verilog/verilog_module_writer.h+5-5
- openfpga/src/fpga_verilog/verilog_mux.cpp+24-21
- openfpga/src/fpga_verilog/verilog_routing.cpp+2-6
- openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp+2-6
- openfpga/src/fpga_verilog/verilog_tile.cpp+1-3
- openfpga/src/fpga_verilog/verilog_top_module.cpp+2-6
- openfpga/src/fpga_verilog/verilog_writer_utils.cpp+18
- openfpga/src/fpga_verilog/verilog_writer_utils.h+4
- openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga+73
- openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh+7
- openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf+37
- openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf+37
- openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf+37
- openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf+37
- openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf+37
- openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf+37
- yosys+1-1
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