Skip to content

Commit c95c3e2

Browse files
authored
Merge pull request #898 from os-fpga/checker_impr_primDB_better_warning
checker: improve primDB for RAM18KX2, better warning about dangling bits
2 parents e474416 + 3f68fe0 commit c95c3e2

File tree

5 files changed

+137
-27
lines changed

5 files changed

+137
-27
lines changed

planning/src/RS/rsCheck.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ bool do_check_blif(CStr cfn,
1919

2020
BLIF_file bfile(string{cfn});
2121

22-
if (tr >= 4)
22+
if (tr >= 3)
2323
bfile.setTrace(tr);
2424

2525
bool exi = false;

planning/src/file_io/pln_blif_file.cpp

Lines changed: 60 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,28 @@ CStr BLIF_file::BNode::cPrimType() const noexcept {
197197
return ptype_ == prim::A_ZERO ? "{e}" : pr_enum2str(ptype_);
198198
}
199199

200+
int BLIF_file::findTermByNet(const vector<string>& D, const string& net) noexcept {
201+
assert(not net.empty());
202+
assert(not D.empty());
203+
if (net.empty() or D.empty())
204+
return -1;
205+
206+
int64_t sz = D.size();
207+
assert(sz < INT_MAX);
208+
209+
//lputs();
210+
//logVec(D, " _bnode.D ");
211+
//lputs();
212+
213+
for (int i = sz - 1; i >= 0; i--) {
214+
CStr term = D[i].c_str();
215+
CStr p = ::strchr(term, '=');
216+
if (p and net == p+1)
217+
return i;
218+
}
219+
return -1;
220+
}
221+
200222
bool BLIF_file::readBlif() noexcept {
201223
inputs_.clear();
202224
outputs_.clear();
@@ -507,15 +529,16 @@ bool BLIF_file::checkBlif(vector<string>& badInputs,
507529
if (trace_ >= 8) {
508530
//string written = pr_write_yaml( FIFO36K );
509531
//string written = pr_write_yaml( FIFO18KX2 );
510-
string written = pr_write_yaml( TDP_RAM36K );
532+
//string written = pr_write_yaml( TDP_RAM36K );
533+
string written = pr_write_yaml( TDP_RAM18KX2 );
511534
flush_out(true);
512535
if (written.empty()) {
513536
lprintf("\t\t FAIL: pr_write_yaml() FAILED\n\n");
514537
} else {
515538
lprintf("\t written: %s\n\n", written.c_str());
516539
if (0) {
517540
lprintf("\n ");
518-
for (int bb = 30; bb >= 0; bb--) {
541+
for (int bb = 15; bb >= 0; bb--) {
519542
lprintf(" \"RDATA_A[%i]\",", bb);
520543
}
521544
lputs();
@@ -1127,6 +1150,12 @@ bool BLIF_file::createNodes() noexcept {
11271150
if (not starts_w_subckt(cs + 1, len - 1))
11281151
continue;
11291152
Fio::split_spa(lines_[L], V);
1153+
//if (L == 48) {
1154+
// string delWire1151 = "$delete_wire$1151";
1155+
// lputs8();
1156+
// int dTerm = findTermByNet(V, delWire1151);
1157+
// lprintf(" dTerm= %i\n", dTerm);
1158+
//}
11301159
if (V.size() > 1 and V.front() == ".subckt") {
11311160
Prim_t pt = pr_str2enum( V[1].c_str() );
11321161
if (pr_is_MOG(pt)) {
@@ -1172,7 +1201,6 @@ bool BLIF_file::createNodes() noexcept {
11721201
if (starts_w_names(cs + 1, len - 1)) {
11731202
Fio::split_spa(lines_[L], V);
11741203
if (V.size() > 1 and V.front() == ".names") {
1175-
//lputs9();
11761204
nodePool_.emplace_back(".names", L);
11771205
BNode& nd = nodePool_.back();
11781206
nd.data_.assign(V.begin() + 1, V.end());
@@ -1209,7 +1237,6 @@ bool BLIF_file::createNodes() noexcept {
12091237
nd.ptype_ = pr_str2enum(nd.data_front());
12101238
nd.place_output_at_back(nd.data_);
12111239
if (pr_is_DSP(nd.ptype_)) {
1212-
//lputs9();
12131240
vector<string> TK;
12141241
// search for .param DSP_MODE "MULTIPLY"
12151242
// to flag clock-less DSP
@@ -1285,6 +1312,13 @@ bool BLIF_file::createNodes() noexcept {
12851312
continue;
12861313
assert(!nd.is_mog_);
12871314

1315+
//if (nd.lnum_ == 48) {
1316+
// string delWire1151 = "$delete_wire$1151";
1317+
// lputs8();
1318+
// int dTerm = findTermByNet(nd.data_, delWire1151);
1319+
// lprintf(" dTerm= %i\n", dTerm);
1320+
//}
1321+
12881322
s_is_MOG(nd, V);
12891323
bool is_mog = V.size() > 1;
12901324
if (is_mog) {
@@ -1294,15 +1328,16 @@ bool BLIF_file::createNodes() noexcept {
12941328
logVec(V, " [V-terms] ");
12951329
lputs();
12961330
}
1297-
//lputs9();
12981331

1332+
vector<string> dataCopy { nd.data_ };
12991333
s_remove_MOG_terms(nd);
13001334
uint startVirtual = nodePool_.size();
13011335
for (uint j = 1; j < V.size(); j++) {
13021336
nodePool_.emplace_back(nd);
13031337
nodePool_.back().virtualOrigin_ = i;
13041338
nodePool_.back().is_mog_ = true;
13051339
}
1340+
nd.realData_.swap(dataCopy);
13061341
nd.data_.push_back(V.front());
13071342
nd.is_mog_ = true;
13081343
// give one output term to each virtual MOG:
@@ -1341,8 +1376,6 @@ bool BLIF_file::createNodes() noexcept {
13411376
}
13421377
if (nd.kw_ == ".subckt" or nd.kw_ == ".gate") {
13431378
if (nd.data_.size() > 1) {
1344-
// if (nd.lnum_ == 47)
1345-
// lputs8();
13461379
const string& last = nd.data_.back();
13471380
size_t llen = last.length();
13481381
if (!last.empty() and llen < 4095) {
@@ -1637,7 +1670,6 @@ bool BLIF_file::linkNodes() noexcept {
16371670
assert(fab_nd);
16381671
BNode& nd = *fab_nd;
16391672
if (nd.out_.empty()) {
1640-
//lputs8();
16411673
err_msg_ = str::concat("incomplete fabric cell: ", nd.kw_);
16421674
if (!nd.data_.empty()) {
16431675
err_msg_ += str::concat(" ", nd.data_.front());
@@ -1708,20 +1740,35 @@ bool BLIF_file::linkNodes() noexcept {
17081740
assert(!nd.out_.empty());
17091741
if (nd.parent_)
17101742
continue;
1743+
// if (nd.lnum_ == 48)
1744+
// lputs7();
17111745
int pinIndex = -1;
17121746
BNode* par = findFabricParent(nd.id_, nd.out_, pinIndex);
17131747
if (!par) {
17141748
if (nd.is_RAM() or nd.is_DSP()) {
1749+
const string& net = nd.out_;
17151750
bool is_ram = nd.is_RAM();
1751+
uint rid = nd.realId(*this);
1752+
const BNode& realNd = bnodeRef(rid);
1753+
const vector<string>& realData = realNd.realData_;
1754+
assert(not realData.empty());
1755+
int dataTerm = findTermByNet(realData, net);
1756+
assert(dataTerm >= 0);
1757+
assert(dataTerm < int64_t(realData.size()));
1758+
if (dataTerm < 0)
1759+
continue;
17161760
// RAM or DSP output bits may be unused
1717-
if (trace_ >= 5) {
1761+
if (trace_ >= 4) {
17181762
lprintf("skipping dangling cell output issue for %s at line %u\n",
1719-
is_ram ? "RAM" : "DSP", nd.lnum_);
1763+
is_ram ? "RAM" : "DSP", realNd.lnum_);
1764+
lprintf(" dangling net: %s term# %i %s\n",
1765+
net.c_str(), dataTerm, realData[dataTerm].c_str());
1766+
lputs();
17201767
}
17211768
if (is_ram)
1722-
dang_RAM_outputs_.emplace_back(nd.id_);
1769+
dang_RAM_outputs_.emplace_back(realNd.id_, dataTerm);
17231770
else
1724-
dang_DSP_outputs_.emplace_back(nd.id_);
1771+
dang_DSP_outputs_.emplace_back(realNd.id_, dataTerm);
17251772
continue;
17261773
}
17271774
err_msg_ = "dangling cell output: ";
@@ -1934,7 +1981,7 @@ bool BLIF_file::checkClockSepar(vector<BNode*>& clocked) noexcept {
19341981
else
19351982
pg_.setNwName("pin_graph_VIOL");
19361983

1937-
if (trace_ >= 3) {
1984+
if (not ::getenv("pln_blif_dont_write_pinGraph")) {
19381985
pinGraphFile_ = writePinGraph("_PinGraph.dot");
19391986
}
19401987

planning/src/file_io/pln_blif_file.h

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,19 @@ struct BLIF_file : public fio::MMapReader
2828
uint depth_ = 0;
2929
vector<uint> chld_;
3030

31-
string kw_; // keyword: .names, .latch, .subckt, .gate, etc.
32-
vector<string> data_; // everything on the line ater kw, tokenized
31+
string kw_; // keyword: .names, .latch, .subckt, .gate, etc.
3332

34-
vector<string> inPins_; // input pins from Prim-DB
35-
vector<string> inSigs_; // input signals from blif-file
33+
vector<string> realData_; // everything on the line ater kw, tokenized.
34+
// populated only for real MOGs, otherwise use data_
3635

37-
string out_; // SOG output net (=signal) (real or virtual)
36+
vector<string> data_; // like realData_, but has only 1 output term (virtual SOG)
3837

39-
uint virtualOrigin_ = 0; // node-ID from which this virtual MOG is created
38+
vector<string> inPins_; // input pins from Prim-DB
39+
vector<string> inSigs_; // input signals from blif-file
40+
41+
string out_; // SOG output net (=signal) (real or virtual)
42+
43+
uint virtualOrigin_ = 0; // node-ID from which this virtual MOG is created
4044

4145
prim::Prim_t ptype_ = prim::A_ZERO;
4246

@@ -331,15 +335,17 @@ struct BLIF_file : public fio::MMapReader
331335
return F->second;
332336
}
333337

338+
static int findTermByNet(const vector<string>& D, const string& net) noexcept; // index in BNode::data_
339+
334340
// DATA:
335341
std::vector<BNode> nodePool_; // nodePool_[0] is a fake node "parent of root"
336342

337343
std::vector<BNode*> topInputs_, topOutputs_;
338344
std::vector<BNode*> fabricNodes_, constantNodes_;
339345
std::vector<BNode*> fabricRealNodes_; // skip virtual SOGs
340346

341-
std::vector<uint> dang_RAM_outputs_;
342-
std::vector<uint> dang_DSP_outputs_;
347+
std::vector<upair> dang_RAM_outputs_; // (nid, dataTerm)
348+
std::vector<upair> dang_DSP_outputs_; // (nid, dataTerm)
343349

344350
std::vector<BNode*> latches_; // latches are not checked for now
345351

planning/src/file_io/pln_primitives.cpp

Lines changed: 61 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -184,13 +184,49 @@ using std::string;
184184
"CLK_OUT_DIV3", "CLK_OUT_DIV4",
185185
"SERDES_FAST_CLK", "LOCK" },
186186

187-
// TDP_RAM18KX2
188-
{ "RDATA_A1", "RDATA_B1", "RDATA_A2", "RDATA_B2",
189-
"RPARITY_A1", "RPARITY_B1", "RPARITY_A2", "RPARITY_B2" },
187+
// ---- TDP_RAM18KX2
188+
{
189+
// RDATA_A1[15:0]:
190+
"RDATA_A1[15]", "RDATA_A1[14]", "RDATA_A1[13]", "RDATA_A1[12]", "RDATA_A1[11]", "RDATA_A1[10]",
191+
"RDATA_A1[9]", "RDATA_A1[8]", "RDATA_A1[7]", "RDATA_A1[6]", "RDATA_A1[5]", "RDATA_A1[4]",
192+
"RDATA_A1[3]", "RDATA_A1[2]", "RDATA_A1[1]", "RDATA_A1[0]",
193+
194+
// RPARITY_A1[1:0]:
195+
// default: "{2{1'b0}}"
196+
"RPARITY_A1[1]", "RPARITY_A1[0]",
197+
198+
// RDATA_B1[15:0]:
199+
"RDATA_B1[15]", "RDATA_B1[14]", "RDATA_B1[13]", "RDATA_B1[12]", "RDATA_B1[11]", "RDATA_B1[10]",
200+
"RDATA_B1[9]", "RDATA_B1[8]", "RDATA_B1[7]", "RDATA_B1[6]", "RDATA_B1[5]", "RDATA_B1[4]",
201+
"RDATA_B1[3]", "RDATA_B1[2]", "RDATA_B1[1]", "RDATA_B1[0]",
202+
203+
// RPARITY_B1[1:0]:
204+
// default: "{2{1'b0}}"
205+
"RPARITY_B1[1]", "RPARITY_B1[0]",
206+
207+
// RDATA_A2[15:0]:
208+
"RDATA_A2[15]", "RDATA_A2[14]", "RDATA_A2[13]", "RDATA_A2[12]", "RDATA_A2[11]", "RDATA_A2[10]",
209+
"RDATA_A2[9]", "RDATA_A2[8]", "RDATA_A2[7]", "RDATA_A2[6]", "RDATA_A2[5]", "RDATA_A2[4]",
210+
"RDATA_A2[3]", "RDATA_A2[2]", "RDATA_A2[1]", "RDATA_A2[0]",
211+
212+
// RPARITY_A2[1:0]:
213+
// default: "{2{1'b0}}"
214+
"RPARITY_A2[1]", "RPARITY_A2[0]",
215+
216+
// RDATA_B2[15:0]:
217+
"RDATA_B2[15]", "RDATA_B2[14]", "RDATA_B2[13]", "RDATA_B2[12]", "RDATA_B2[11]", "RDATA_B2[10]",
218+
"RDATA_B2[9]", "RDATA_B2[8]", "RDATA_B2[7]", "RDATA_B2[6]", "RDATA_B2[5]", "RDATA_B2[4]",
219+
"RDATA_B2[3]", "RDATA_B2[2]", "RDATA_B2[1]", "RDATA_B2[0]",
220+
221+
// RPARITY_B2[1:0]:
222+
// default: "{2{1'b0}}"
223+
"RPARITY_B2[1]", "RPARITY_B2[0]"
224+
},
190225

191226
// TDP_RAM36K
192227
{
193228
// RDATA_A[31:0]
229+
"RDATA_A[31]",
194230
"RDATA_A[30]", "RDATA_A[29]", "RDATA_A[28]", "RDATA_A[27]", "RDATA_A[26]", "RDATA_A[25]",
195231
"RDATA_A[24]", "RDATA_A[23]", "RDATA_A[22]", "RDATA_A[21]", "RDATA_A[20]", "RDATA_A[19]",
196232
"RDATA_A[18]", "RDATA_A[17]", "RDATA_A[16]", "RDATA_A[15]", "RDATA_A[14]", "RDATA_A[13]",
@@ -199,6 +235,7 @@ using std::string;
199235
"RDATA_A[1]", "RDATA_A[0]",
200236

201237
// RDATA_B[31:0]
238+
"RDATA_B[31]",
202239
"RDATA_B[30]", "RDATA_B[29]", "RDATA_B[28]", "RDATA_B[27]", "RDATA_B[26]", "RDATA_B[25]",
203240
"RDATA_B[24]", "RDATA_B[23]", "RDATA_B[22]", "RDATA_B[21]", "RDATA_B[20]", "RDATA_B[19]",
204241
"RDATA_B[18]", "RDATA_B[17]", "RDATA_B[16]", "RDATA_B[15]", "RDATA_B[14]", "RDATA_B[13]",
@@ -379,7 +416,27 @@ using std::string;
379416
// PLL
380417
{ "PLL_EN", "CLK_IN" },
381418

382-
// TDP_RAM18KX2 // TMP. INCOMPLETE
419+
// ---- TDP_RAM18KX2 // TMP. INCOMPLETE
420+
// WEN_A1:
421+
// dir: input
422+
// desc: Write-enable port A, RAM 1
423+
// WEN_B1:
424+
// dir: input
425+
// desc: Write-enable port B, RAM 1
426+
// REN_A1:
427+
// dir: input
428+
// desc: Read-enable port A, RAM 1
429+
// REN_B1:
430+
// dir: input
431+
// desc: Read-enable port B, RAM 1
432+
// CLK_A1:
433+
// dir: input
434+
// desc: Clock port A, RAM 1
435+
// bb_attributes: clkbuf_sink
436+
// CLK_B1:
437+
// dir: input
438+
// desc: Clock port B, RAM 1
439+
// bb_attributes: clkbuf_sink
383440
{ "WEN_A1", "WEN_B1", "REN_A1", "REN_B1",
384441
"CLK_A1", "CLK_B1" },
385442

planning/src/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
static const char* _pln_VERSION_STR = "pln0352";
1+
static const char* _pln_VERSION_STR = "pln0353";
22

33
#include "RS/rsEnv.h"
44
#include "util/pln_log.h"

0 commit comments

Comments
 (0)