Merge pull request #898 from os-fpga/checker_impr_primDB_better_warning

checker: improve primDB for RAM18KX2, better warning about dangling bits

Author: serge-dsa

planning/src/RS/rsCheck.cpp

@@ -19,7 +19,7 @@ bool do_check_blif(CStr cfn,
 
   BLIF_file bfile(string{cfn});
 
-  if (tr >= 4)
+  if (tr >= 3)
     bfile.setTrace(tr);
 
   bool exi = false;

planning/src/file_io/pln_blif_file.cpp

@@ -197,6 +197,28 @@ CStr BLIF_file::BNode::cPrimType() const noexcept {
   return ptype_ == prim::A_ZERO ? "{e}" : pr_enum2str(ptype_);
 }
 
+int BLIF_file::findTermByNet(const vector<string>& D, const string& net) noexcept {
+  assert(not net.empty());
+  assert(not D.empty());
+  if (net.empty() or D.empty())
+    return -1;
+
+  int64_t sz = D.size();
+  assert(sz < INT_MAX);
+
+  //lputs();
+  //logVec(D, " _bnode.D ");
+  //lputs();
+
+  for (int i = sz - 1; i >= 0; i--) {
+    CStr term = D[i].c_str();
+    CStr p = ::strchr(term, '=');
+    if (p and net == p+1)
+      return i;
+  }
+  return -1;
+}
+
 bool BLIF_file::readBlif() noexcept {
   inputs_.clear();
   outputs_.clear();
@@ -507,15 +529,16 @@ bool BLIF_file::checkBlif(vector<string>& badInputs,
   if (trace_ >= 8) {
     //string written = pr_write_yaml( FIFO36K );
     //string written = pr_write_yaml( FIFO18KX2 );
-    string written = pr_write_yaml( TDP_RAM36K );
+    //string written = pr_write_yaml( TDP_RAM36K );
+    string written = pr_write_yaml( TDP_RAM18KX2 );
     flush_out(true);
     if (written.empty()) {
       lprintf("\t\t  FAIL: pr_write_yaml() FAILED\n\n");
     } else {
       lprintf("\t  written: %s\n\n", written.c_str());
       if (0) {
         lprintf("\n    ");
-        for (int bb = 30; bb >= 0; bb--) {
+        for (int bb = 15; bb >= 0; bb--) {
           lprintf(" \"RDATA_A[%i]\",", bb);
         }
         lputs();
@@ -1127,6 +1150,12 @@ bool BLIF_file::createNodes() noexcept {
       if (not starts_w_subckt(cs + 1, len - 1))
         continue;
       Fio::split_spa(lines_[L], V);
+      //if (L == 48) {
+      //  string delWire1151 = "$delete_wire$1151";
+      //  lputs8();
+      //  int dTerm = findTermByNet(V, delWire1151);
+      //  lprintf("  dTerm= %i\n", dTerm);
+      //}
       if (V.size() > 1 and V.front() == ".subckt") {
         Prim_t pt = pr_str2enum( V[1].c_str() );
         if (pr_is_MOG(pt)) {
@@ -1172,7 +1201,6 @@ bool BLIF_file::createNodes() noexcept {
     if (starts_w_names(cs + 1, len - 1)) {
       Fio::split_spa(lines_[L], V);
       if (V.size() > 1 and V.front() == ".names") {
-        //lputs9();
         nodePool_.emplace_back(".names", L);
         BNode& nd = nodePool_.back();
         nd.data_.assign(V.begin() + 1, V.end());
@@ -1209,7 +1237,6 @@ bool BLIF_file::createNodes() noexcept {
         nd.ptype_ = pr_str2enum(nd.data_front());
         nd.place_output_at_back(nd.data_);
         if (pr_is_DSP(nd.ptype_)) {
-          //lputs9();
           vector<string> TK;
           // search for .param DSP_MODE "MULTIPLY"
           // to flag clock-less DSP
@@ -1285,6 +1312,13 @@ bool BLIF_file::createNodes() noexcept {
       continue;
     assert(!nd.is_mog_);
 
+    //if (nd.lnum_ == 48) {
+    //  string delWire1151 = "$delete_wire$1151";
+    //  lputs8();
+    //  int dTerm = findTermByNet(nd.data_, delWire1151);
+    //  lprintf("  dTerm= %i\n", dTerm);
+    //}
+
     s_is_MOG(nd, V);
     bool is_mog = V.size() > 1;
     if (is_mog) {
@@ -1294,15 +1328,16 @@ bool BLIF_file::createNodes() noexcept {
         logVec(V, "  [V-terms] ");
         lputs();
       }
-      //lputs9();
 
+      vector<string> dataCopy { nd.data_ };
       s_remove_MOG_terms(nd);
       uint startVirtual = nodePool_.size();
       for (uint j = 1; j < V.size(); j++) {
         nodePool_.emplace_back(nd);
         nodePool_.back().virtualOrigin_ = i;
         nodePool_.back().is_mog_ = true;
       }
+      nd.realData_.swap(dataCopy);
       nd.data_.push_back(V.front());
       nd.is_mog_ = true;
       // give one output term to each virtual MOG:
@@ -1341,8 +1376,6 @@ bool BLIF_file::createNodes() noexcept {
     }
     if (nd.kw_ == ".subckt" or nd.kw_ == ".gate") {
       if (nd.data_.size() > 1) {
-        // if (nd.lnum_ == 47)
-        //   lputs8();
         const string& last = nd.data_.back();
         size_t llen = last.length();
         if (!last.empty() and llen < 4095) {
@@ -1637,7 +1670,6 @@ bool BLIF_file::linkNodes() noexcept {
     assert(fab_nd);
     BNode& nd = *fab_nd;
     if (nd.out_.empty()) {
-      //lputs8();
       err_msg_ = str::concat("incomplete fabric cell:  ", nd.kw_);
       if (!nd.data_.empty()) {
         err_msg_ += str::concat("  ", nd.data_.front());
@@ -1708,20 +1740,35 @@ bool BLIF_file::linkNodes() noexcept {
     assert(!nd.out_.empty());
     if (nd.parent_)
       continue;
+    // if (nd.lnum_ == 48)
+    //   lputs7();
     int pinIndex = -1;
     BNode* par = findFabricParent(nd.id_, nd.out_, pinIndex);
     if (!par) {
       if (nd.is_RAM() or nd.is_DSP()) {
+        const string& net = nd.out_;
         bool is_ram = nd.is_RAM();
+        uint rid = nd.realId(*this);
+        const BNode& realNd = bnodeRef(rid);
+        const vector<string>& realData = realNd.realData_;
+        assert(not realData.empty());
+        int dataTerm = findTermByNet(realData, net);
+        assert(dataTerm >= 0);
+        assert(dataTerm < int64_t(realData.size()));
+        if (dataTerm < 0)
+          continue;
         // RAM or DSP output bits may be unused
-        if (trace_ >= 5) {
+        if (trace_ >= 4) {
           lprintf("skipping dangling cell output issue for %s at line %u\n",
-                  is_ram ? "RAM" : "DSP", nd.lnum_);
+                  is_ram ? "RAM" : "DSP", realNd.lnum_);
+          lprintf("  dangling net: %s  term# %i %s\n",
+                  net.c_str(), dataTerm, realData[dataTerm].c_str());
+          lputs();
         }
         if (is_ram)
-          dang_RAM_outputs_.emplace_back(nd.id_);
+          dang_RAM_outputs_.emplace_back(realNd.id_, dataTerm);
         else
-          dang_DSP_outputs_.emplace_back(nd.id_);
+          dang_DSP_outputs_.emplace_back(realNd.id_, dataTerm);
         continue;
       }
       err_msg_ = "dangling cell output: ";
@@ -1934,7 +1981,7 @@ bool BLIF_file::checkClockSepar(vector<BNode*>& clocked) noexcept {
   else
     pg_.setNwName("pin_graph_VIOL");
 
-  if (trace_ >= 3) {
+  if (not ::getenv("pln_blif_dont_write_pinGraph")) {
     pinGraphFile_ = writePinGraph("_PinGraph.dot");
   }
 

planning/src/file_io/pln_blif_file.h

@@ -28,15 +28,19 @@ struct BLIF_file : public fio::MMapReader
     uint depth_ = 0;
     vector<uint> chld_;
 
-    string kw_;              // keyword: .names, .latch, .subckt, .gate, etc.
-    vector<string> data_;    // everything on the line ater kw, tokenized
+    string kw_;               // keyword: .names, .latch, .subckt, .gate, etc.
 
-    vector<string> inPins_;  // input pins from Prim-DB
-    vector<string> inSigs_;  // input signals from blif-file
+    vector<string> realData_; // everything on the line ater kw, tokenized.
+                              // populated only for real MOGs, otherwise use data_
 
-    string out_;             // SOG output net (=signal) (real or virtual)
+    vector<string> data_;     // like realData_, but has only 1 output term (virtual SOG)
 
-    uint virtualOrigin_ = 0; // node-ID from which this virtual MOG is created
+    vector<string> inPins_;   // input pins from Prim-DB
+    vector<string> inSigs_;   // input signals from blif-file
+
+    string out_;              // SOG output net (=signal) (real or virtual)
+
+    uint virtualOrigin_ = 0;  // node-ID from which this virtual MOG is created
 
     prim::Prim_t  ptype_ = prim::A_ZERO;
 
@@ -331,15 +335,17 @@ struct BLIF_file : public fio::MMapReader
     return F->second;
   }
 
+  static int findTermByNet(const vector<string>& D, const string& net) noexcept; // index in BNode::data_
+
 // DATA:
   std::vector<BNode> nodePool_;  // nodePool_[0] is a fake node "parent of root"
 
   std::vector<BNode*> topInputs_, topOutputs_;
   std::vector<BNode*> fabricNodes_, constantNodes_;
   std::vector<BNode*> fabricRealNodes_; // skip virtual SOGs
 
-  std::vector<uint> dang_RAM_outputs_;
-  std::vector<uint> dang_DSP_outputs_;
+  std::vector<upair> dang_RAM_outputs_; // (nid, dataTerm)
+  std::vector<upair> dang_DSP_outputs_; // (nid, dataTerm)
 
   std::vector<BNode*> latches_; // latches are not checked for now
 

planning/src/file_io/pln_primitives.cpp

@@ -184,13 +184,49 @@ using std::string;
       "CLK_OUT_DIV3", "CLK_OUT_DIV4",
       "SERDES_FAST_CLK", "LOCK" },
 
-    // TDP_RAM18KX2
-    { "RDATA_A1", "RDATA_B1", "RDATA_A2", "RDATA_B2",
-      "RPARITY_A1", "RPARITY_B1", "RPARITY_A2", "RPARITY_B2" },
+    // ---- TDP_RAM18KX2
+    {
+      // RDATA_A1[15:0]:
+      "RDATA_A1[15]", "RDATA_A1[14]", "RDATA_A1[13]", "RDATA_A1[12]", "RDATA_A1[11]", "RDATA_A1[10]",
+      "RDATA_A1[9]", "RDATA_A1[8]", "RDATA_A1[7]", "RDATA_A1[6]", "RDATA_A1[5]", "RDATA_A1[4]",
+      "RDATA_A1[3]", "RDATA_A1[2]", "RDATA_A1[1]", "RDATA_A1[0]",
+
+       // RPARITY_A1[1:0]:
+       //  default: "{2{1'b0}}"
+      "RPARITY_A1[1]", "RPARITY_A1[0]",
+
+      // RDATA_B1[15:0]:
+      "RDATA_B1[15]", "RDATA_B1[14]", "RDATA_B1[13]", "RDATA_B1[12]", "RDATA_B1[11]", "RDATA_B1[10]",
+      "RDATA_B1[9]", "RDATA_B1[8]", "RDATA_B1[7]", "RDATA_B1[6]", "RDATA_B1[5]", "RDATA_B1[4]",
+      "RDATA_B1[3]", "RDATA_B1[2]", "RDATA_B1[1]", "RDATA_B1[0]",
+
+       // RPARITY_B1[1:0]:
+       //  default: "{2{1'b0}}"
+      "RPARITY_B1[1]", "RPARITY_B1[0]",
+
+      // RDATA_A2[15:0]:
+      "RDATA_A2[15]", "RDATA_A2[14]", "RDATA_A2[13]", "RDATA_A2[12]", "RDATA_A2[11]", "RDATA_A2[10]",
+      "RDATA_A2[9]", "RDATA_A2[8]", "RDATA_A2[7]", "RDATA_A2[6]", "RDATA_A2[5]", "RDATA_A2[4]",
+      "RDATA_A2[3]", "RDATA_A2[2]", "RDATA_A2[1]", "RDATA_A2[0]",
+
+       // RPARITY_A2[1:0]:
+       //  default: "{2{1'b0}}"
+      "RPARITY_A2[1]", "RPARITY_A2[0]",
+
+      // RDATA_B2[15:0]:
+      "RDATA_B2[15]", "RDATA_B2[14]", "RDATA_B2[13]", "RDATA_B2[12]", "RDATA_B2[11]", "RDATA_B2[10]",
+      "RDATA_B2[9]", "RDATA_B2[8]", "RDATA_B2[7]", "RDATA_B2[6]", "RDATA_B2[5]", "RDATA_B2[4]",
+      "RDATA_B2[3]", "RDATA_B2[2]", "RDATA_B2[1]", "RDATA_B2[0]",
+
+       // RPARITY_B2[1:0]:
+       //  default: "{2{1'b0}}"
+      "RPARITY_B2[1]", "RPARITY_B2[0]"
+    },
 
     // TDP_RAM36K
     {
       // RDATA_A[31:0]
+      "RDATA_A[31]",
       "RDATA_A[30]", "RDATA_A[29]", "RDATA_A[28]", "RDATA_A[27]", "RDATA_A[26]", "RDATA_A[25]",
       "RDATA_A[24]", "RDATA_A[23]", "RDATA_A[22]", "RDATA_A[21]", "RDATA_A[20]", "RDATA_A[19]",
       "RDATA_A[18]", "RDATA_A[17]", "RDATA_A[16]", "RDATA_A[15]", "RDATA_A[14]", "RDATA_A[13]",
@@ -199,6 +235,7 @@ using std::string;
       "RDATA_A[1]", "RDATA_A[0]",
 
       // RDATA_B[31:0]
+      "RDATA_B[31]",
       "RDATA_B[30]", "RDATA_B[29]", "RDATA_B[28]", "RDATA_B[27]", "RDATA_B[26]", "RDATA_B[25]",
       "RDATA_B[24]", "RDATA_B[23]", "RDATA_B[22]", "RDATA_B[21]", "RDATA_B[20]", "RDATA_B[19]",
       "RDATA_B[18]", "RDATA_B[17]", "RDATA_B[16]", "RDATA_B[15]", "RDATA_B[14]", "RDATA_B[13]",
@@ -379,7 +416,27 @@ using std::string;
     // PLL
     { "PLL_EN", "CLK_IN" },
 
-    // TDP_RAM18KX2  // TMP. INCOMPLETE
+    // ---- TDP_RAM18KX2  // TMP. INCOMPLETE
+    // WEN_A1:
+    //   dir: input
+    //   desc: Write-enable port A, RAM 1
+    // WEN_B1:
+    //   dir: input
+    //   desc: Write-enable port B, RAM 1
+    // REN_A1:
+    //   dir: input
+    //   desc: Read-enable port A, RAM 1
+    // REN_B1:
+    //   dir: input
+    //   desc: Read-enable port B, RAM 1
+    // CLK_A1:
+    //   dir: input
+    //   desc: Clock port A, RAM 1
+    //   bb_attributes: clkbuf_sink
+    // CLK_B1:
+    //   dir: input
+    //   desc: Clock port B, RAM 1
+    //   bb_attributes: clkbuf_sink
     { "WEN_A1", "WEN_B1", "REN_A1", "REN_B1",
       "CLK_A1", "CLK_B1" },
 

planning/src/main.cpp

@@ -1,4 +1,4 @@
-static const char* _pln_VERSION_STR = "pln0352";
+static const char* _pln_VERSION_STR = "pln0353";
 
 #include "RS/rsEnv.h"
 #include "util/pln_log.h"