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finish pb_fixup and readoptions merge
1 parent 346aad4 commit c7f06fd

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4 files changed

+90
-57
lines changed

4 files changed

+90
-57
lines changed

CMakeLists.txt

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,11 @@ FILE(COPY ${EBLIF_TRANSFORM_SRC_H}
130130
DESTINATION
131131
${EBLIF_TRANSFORM_DEST})
132132

133+
message(STATUS "NOTE: PATCHING VPR pack/pb_pin_fixup\n")
134+
FILE(COPY ${PACKER_SRC_DIR}/post_routing_pb_pin_fixup.cpp
135+
DESTINATION
136+
${VPR_DEST_DIR}/src/pack)
137+
133138
# patch VPR
134139
#FILE(COPY ${PACKER_SRC_DIR}/cluster.cpp
135140
# ${PACKER_SRC_DIR}/cluster_util.cpp

include/base_fix/PATCHED/read_options.cpp

Lines changed: 42 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,14 @@ struct ParseCircuitFormat {
101101
conv_value.set_value(e_circuit_format::BLIF);
102102
else if (str == "eblif")
103103
conv_value.set_value(e_circuit_format::EBLIF);
104+
else if (str == "verilog")
105+
conv_value.set_value(e_circuit_format::VERILOG);
106+
else if (str == "edif")
107+
conv_value.set_value(e_circuit_format::EDIF);
108+
else if (str == "edf")
109+
conv_value.set_value(e_circuit_format::EDIF);
110+
else if (str == "edn")
111+
conv_value.set_value(e_circuit_format::EDIF);
104112
else if (str == "fpga-interchange")
105113
conv_value.set_value(e_circuit_format::FPGA_INTERCHANGE);
106114
else {
@@ -120,6 +128,10 @@ struct ParseCircuitFormat {
120128
conv_value.set_value("blif");
121129
else if (val == e_circuit_format::EBLIF)
122130
conv_value.set_value("eblif");
131+
else if (val == e_circuit_format::VERILOG)
132+
conv_value.set_value("verilog");
133+
else if (val == e_circuit_format::EDIF)
134+
conv_value.set_value("edif");
123135
else {
124136
VTR_ASSERT(val == e_circuit_format::FPGA_INTERCHANGE);
125137
conv_value.set_value("fpga-interchange");
@@ -129,7 +141,7 @@ struct ParseCircuitFormat {
129141
}
130142

131143
std::vector<std::string> default_choices() {
132-
return {"auto", "blif", "eblif", "fpga-interchange"};
144+
return {"auto", "blif", "eblif", "verilog", "edif", "edn", "edf", "fpga-interchange"};
133145
}
134146
};
135147
struct ParseRoutePredictor {
@@ -398,6 +410,8 @@ struct ParsePlaceAlgorithm {
398410
conv_value.set_value(CRITICALITY_TIMING_PLACE);
399411
} else if (str == "slack_timing") {
400412
conv_value.set_value(SLACK_TIMING_PLACE);
413+
} else if (str == "congestion_aware") {
414+
conv_value.set_value(CONGESTION_AWARE_PLACE);
401415
} else {
402416
std::stringstream msg;
403417
msg << "Invalid conversion from '" << str << "' to e_place_algorithm (expected one of: " << argparse::join(default_choices(), ", ") << ")";
@@ -419,6 +433,8 @@ struct ParsePlaceAlgorithm {
419433
conv_value.set_value("bounding_box");
420434
} else if (val == CRITICALITY_TIMING_PLACE) {
421435
conv_value.set_value("criticality_timing");
436+
} else if (val == CONGESTION_AWARE_PLACE) {
437+
conv_value.set_value("congestion_aware");
422438
} else {
423439
VTR_ASSERT(val == SLACK_TIMING_PLACE);
424440
conv_value.set_value("slack_timing");
@@ -427,7 +443,7 @@ struct ParsePlaceAlgorithm {
427443
}
428444

429445
std::vector<std::string> default_choices() {
430-
return {"bounding_box", "criticality_timing", "slack_timing"};
446+
return {"bounding_box", "criticality_timing", "slack_timing", "congestion_aware"};
431447
}
432448
};
433449

@@ -1432,6 +1448,10 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
14321448
.help("Show this help message then exit")
14331449
.action(argparse::Action::HELP);
14341450

1451+
gen_grp.add_argument(args.top_mod, "--top", "-t")
1452+
.help("Top module name")
1453+
.default_value("");
1454+
14351455
gen_grp.add_argument<bool, ParseOnOff>(args.show_version, "--version")
14361456
.help("Show version information then exit")
14371457
.action(argparse::Action::VERSION);
@@ -1909,6 +1929,16 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
19091929
.default_value("semiDirectedSwap")
19101930
.show_in(argparse::ShowIn::HELP_ONLY);
19111931

1932+
pack_grp.add_argument<bool, ParseOnOff>(args.use_partitioning_in_pack, "--use_partitioning_in_pack")
1933+
.help("Whether to use partitioning in pack.")
1934+
.default_value("off")
1935+
.show_in(argparse::ShowIn::HELP_ONLY);
1936+
1937+
pack_grp.add_argument<int>(args.number_of_molecules_in_partition, "--number_of_molecules_in_partition")
1938+
.help("Average number of molecules in each cluster. It should be used when --use_partitioning_in_pack is on.")
1939+
.default_value("64")
1940+
.show_in(argparse::ShowIn::HELP_ONLY);
1941+
19121942
auto& place_grp = parser.add_argument_group("placement options");
19131943

19141944
place_grp.add_argument(args.Seed, "--seed")
@@ -2014,7 +2044,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
20142044
" * criticality_timing: Focuses on minimizing both the wirelength and the connection timing costs (criticality * delay).\n"
20152045
" * slack_timing: Focuses on improving the circuit slack values to reduce critical path delay.\n")
20162046
.default_value("criticality_timing")
2017-
.choices({"bounding_box", "criticality_timing", "slack_timing"})
2047+
.choices({"bounding_box", "criticality_timing", "slack_timing", "congestion_aware"})
20182048
.show_in(argparse::ShowIn::HELP_ONLY);
20192049

20202050
place_grp.add_argument<e_place_algorithm, ParsePlaceAlgorithm>(args.PlaceQuenchAlgorithm, "--place_quench_algorithm")
@@ -2026,7 +2056,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
20262056
" * criticality_timing: Focuses on minimizing both the wirelength and the connection timing costs (criticality * delay).\n"
20272057
" * slack_timing: Focuses on improving the circuit slack values to reduce critical path delay.\n")
20282058
.default_value("criticality_timing")
2029-
.choices({"bounding_box", "criticality_timing", "slack_timing"})
2059+
.choices({"bounding_box", "criticality_timing", "slack_timing", "congestion_aware"})
20302060
.show_in(argparse::ShowIn::HELP_ONLY);
20312061

20322062
place_grp.add_argument(args.PlaceChanWidth, "--place_chan_width")
@@ -2064,6 +2094,14 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
20642094
.default_value("false")
20652095
.show_in(argparse::ShowIn::HELP_ONLY);
20662096

2097+
// Cascade Placer
2098+
place_grp.add_argument(args.enable_cascade_placer, "--enable_cascade_placer")
2099+
.help(
2100+
"Enables the cascade placer. "
2101+
"Once analytic placement is done, the result is passed through the annealing (SA) placer")
2102+
.default_value("false")
2103+
.show_in(argparse::ShowIn::HELP_ONLY);
2104+
20672105
place_grp.add_argument(args.place_static_move_prob, "--place_static_move_prob")
20682106
.help(
20692107
"The percentage probabilities of different moves in Simulated Annealing placement. "

include/packer_fix/post_routing_pb_pin_fixup.cpp

Lines changed: 42 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ static bool check_pb_route_for_block(ClusterBlockId clb_id,
8080
PB_route_error& err) {
8181
err.reset();
8282
err.clb_id_ = clb_id;
83-
err.clbLoc_ = plCon.block_locs[clb_id];
83+
err.clbLoc_ = plCon.block_locs()[clb_id];
8484

8585
const t_pb& clb = *clCon.clb_nlist.block_pb(clb_id);
8686
VTR_ASSERT(clb.name);
@@ -260,7 +260,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li
260260
* Deposit all the sides
261261
*/
262262
if (wanted_sides.empty()) {
263-
for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) {
263+
for (e_side side : TOTAL_2D_SIDES) {
264264
wanted_sides.push_back(side);
265265
}
266266
}
@@ -309,55 +309,49 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li
309309
ParentNetId routing_net_id = ParentNetId::INVALID();
310310
std::vector<RRNodeId> visited_rr_nodes;
311311
short valid_routing_net_cnt = 0;
312-
int addToY = 0, addToX = 0;
313-
addToY = physical_tile->height;
314-
addToX = physical_tile->width;
315-
for (int ix = 0; ix < addToX; ix++) {
316-
for (int iy = 0; iy < addToY; iy++) {
317-
for (const e_side& pin_side : pin_sides) {
318-
/* Find the net mapped to this pin in routing results */
319-
RRNodeId rr_node = node_lookup.find_node(coord_layer, coord_x + ix, coord_y + iy, rr_node_type, physical_pin, pin_side);
320-
321-
/* Bypass invalid nodes, after that we must have a valid rr_node id */
322-
if (!rr_node) {
323-
continue;
324-
}
325-
VTR_ASSERT((size_t)rr_node < device_ctx.rr_graph.num_nodes());
312+
for (const e_side& pin_side : pin_sides) {
313+
/* Find the net mapped to this pin in routing results */
314+
RRNodeId rr_node = node_lookup.find_node(coord_layer, coord_x, coord_y, rr_node_type, physical_pin, pin_side);
326315

327-
/* If the node has been visited on the other side, we just skip it */
328-
if (visited_rr_nodes.end() != std::find(visited_rr_nodes.begin(), visited_rr_nodes.end(), RRNodeId(rr_node))) {
329-
continue;
330-
}
316+
/* Bypass invalid nodes, after that we must have a valid rr_node id */
317+
if (!rr_node) {
318+
continue;
319+
}
320+
VTR_ASSERT((size_t)rr_node < device_ctx.rr_graph.num_nodes());
331321

332-
/* Get the cluster net id which has been mapped to this net
333-
* In general, there is only one valid rr_node among all the sides.
334-
* However, we have an exception in the Stratix-IV arch modeling,
335-
* where a pb_pin may exist in two different sides but
336-
* router will only map to 1 rr_node
337-
* Therefore, it is better to compare the routing nets
338-
* for all the sides and pick
339-
* - The unique valid net id (others should be all invalid)
340-
* assume that this pin is used by router
341-
* - A invalid net id (others should be all invalid as well)
342-
* assume that this pin is not used by router
343-
*/
344-
if (rr_node_nets[rr_node]) {
345-
if (routing_net_id) {
346-
if (routing_net_id != rr_node_nets[rr_node]) {
347-
VTR_LOG_ERROR("Pin '%s' is mapped to two nets: '%s' and '%s'\n",
348-
pb_graph_pin->to_string().c_str(),
349-
net_list.net_name(routing_net_id).c_str(),
350-
net_list.net_name(rr_node_nets[rr_node]).c_str());
351-
}
352-
VTR_ASSERT(routing_net_id == rr_node_nets[rr_node]);
353-
}
354-
routing_net_id = rr_node_nets[rr_node];
355-
valid_routing_net_cnt++;
356-
visited_rr_nodes.push_back(rr_node);
322+
/* If the node has been visited on the other side, we just skip it */
323+
if (visited_rr_nodes.end() != std::find(visited_rr_nodes.begin(), visited_rr_nodes.end(), RRNodeId(rr_node))) {
324+
continue;
325+
}
326+
327+
/* Get the cluster net id which has been mapped to this net
328+
* In general, there is only one valid rr_node among all the sides.
329+
* However, we have an exception in the Stratix-IV arch modeling,
330+
* where a pb_pin may exist in two different sides but
331+
* router will only map to 1 rr_node
332+
* Therefore, it is better to compare the routing nets
333+
* for all the sides and pick
334+
* - The unique valid net id (others should be all invalid)
335+
* assume that this pin is used by router
336+
* - A invalid net id (others should be all invalid as well)
337+
* assume that this pin is not used by router
338+
*/
339+
if (rr_node_nets[rr_node]) {
340+
if (routing_net_id) {
341+
if (routing_net_id != rr_node_nets[rr_node]) {
342+
VTR_LOG_ERROR("Pin '%s' is mapped to two nets: '%s' and '%s'\n",
343+
pb_graph_pin->to_string().c_str(),
344+
net_list.net_name(routing_net_id).c_str(),
345+
net_list.net_name(rr_node_nets[rr_node]).c_str());
357346
}
347+
VTR_ASSERT(routing_net_id == rr_node_nets[rr_node]);
358348
}
349+
routing_net_id = rr_node_nets[rr_node];
350+
valid_routing_net_cnt++;
351+
visited_rr_nodes.push_back(rr_node);
359352
}
360353
}
354+
361355
VTR_ASSERT((0 == valid_routing_net_cnt) || (1 == valid_routing_net_cnt));
362356

363357
/* Find the net mapped to this pin in clustering results*/
@@ -935,8 +929,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom
935929
*/
936930
VTR_ASSERT(sink_pb_route == sink_pb_pin_to_add->pin_count_in_cluster);
937931
t_pb_graph_pin* new_sink_pb_pin_to_add = sink_pb_pin_to_add;
938-
//VTR_ASSERT(is_single_fanout_pb_pin(const_cast<const t_pb_graph_pin*>(new_sink_pb_pin_to_add)));
939-
VTR_ASSERT(new_sink_pb_pin_to_add->output_edges[0]->num_output_pins == 1);
932+
VTR_ASSERT(is_single_fanout_pb_pin(const_cast<const t_pb_graph_pin*>(new_sink_pb_pin_to_add)));
940933
int new_driver_pb_pin = pb_graph_pin->pin_count_in_cluster;
941934
while (1) {
942935
int new_sink_pb_route_id = new_sink_pb_pin_to_add->pin_count_in_cluster;
@@ -1045,7 +1038,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom
10451038
for (int& sink_pb_route : new_pb_route.sink_pb_pin_ids) {
10461039
usedItems.push_back(sink_pb_route);
10471040
}
1048-
1041+
10491042
VTR_LOGV(verbose,
10501043
"Remap clustered block '%s' routing trace[%d] to net '%s'\n",
10511044
clustering_ctx.clb_nlist.block_pb(blk_id)->name,
@@ -1264,18 +1257,15 @@ void sync_netlists_to_routing(const Netlist<>& net_list,
12641257
clb_blk_id = convert_to_cluster_block_id(blk_id);
12651258
}
12661259
VTR_ASSERT(clb_blk_id != ClusterBlockId::INVALID());
1267-
// vtr::Point<size_t> grid_coord(placement_ctx.block_locs[clb_blk_id].loc.x,
1268-
// placement_ctx.block_locs[clb_blk_id].loc.y);
12691260

12701261
if (seen_block_ids.insert(clb_blk_id).second) {
12711262
update_cluster_pin_with_post_routing_results(net_list,
12721263
atom_ctx,
12731264
device_ctx,
12741265
clustering_ctx,
12751266
rr_node_nets,
1276-
placement_ctx.block_locs[clb_blk_id].loc,
1267+
placement_ctx.block_locs()[clb_blk_id].loc,
12771268
clb_blk_id,
1278-
// placement_ctx.block_locs[clb_blk_id].loc.sub_tile,
12791269
num_mismatches,
12801270
verbose,
12811271
is_flat);

planning/src/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
static const char* _pln_VERSION_STR = "pln0350";
1+
static const char* _pln_VERSION_STR = "pln0351";
22

33
#include "RS/rsEnv.h"
44
#include "util/pln_log.h"

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