Skip to content

Commit b2d9a33

Browse files
serge-dsaserge-dsa
authored
Merge pull request #712 from os-fpga/checker_update_pin_info
checker: updated pin info based on YAML
2 parents cb7d5b6 + 864c8cf commit b2d9a33

File tree

4 files changed

+135
-25
lines changed

4 files changed

+135
-25
lines changed

‎stars/src/file_readers/pln_blif_file.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -546,6 +546,13 @@ static bool s_is_MOG(const BLIF_file::Node& nd,
546546
if (dsz < 4)
547547
return false;
548548

549+
if (nd.ptype_ == O_SERDES_CLK)
550+
return false;
551+
552+
uint pt = nd.ptype_;
553+
if (pt >= LUT1 and pt <= LUT6)
554+
return false;
555+
549556
if (nd.ptype_ == I_SERDES) {
550557
for (const string& t : data) {
551558
if (is_I_SERDES_output_term(t))
@@ -574,6 +581,13 @@ static bool s_is_MOG(const BLIF_file::Node& nd,
574581
}
575582
return true;
576583
}
584+
if (nd.ptype_ == PLL) {
585+
for (const string& t : data) {
586+
if (is_PLL_output_term(t))
587+
terms.push_back(t);
588+
}
589+
return true;
590+
}
577591

578592
bool has_O = false, has_Y = false, has_Q = false,
579593
has_COUT = false;
@@ -658,6 +672,16 @@ static void s_remove_MOG_terms(BLIF_file::Node& nd) noexcept {
658672
}
659673
return;
660674
}
675+
if (nd.ptype_ == PLL) {
676+
for (uint i = dsz - 1; i > 1; i--) {
677+
const string& t = data[i];
678+
if (is_PLL_output_term(t)) {
679+
data.erase(data.begin() + i);
680+
continue;
681+
}
682+
}
683+
return;
684+
}
661685

662686
for (uint i = dsz - 1; i > 1; i--) {
663687
CStr cs = data[i].c_str();

‎stars/src/file_readers/pln_primitives.cpp

Lines changed: 107 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -82,9 +82,26 @@ namespace {
8282
{ "O" }, // IO_BUF = 13,
8383
{ "O" }, // IO_BUF_DS = 14,
8484

85-
// I_SERDES = 15,
86-
{ "DLY_TAP_VALUE", "CLK_OUT", "CDR_CORE_CLK",
87-
"Q", "DATA_VALID", "DPA_LOCK", "DPA_ERROR" },
85+
86+
/* I_SERDES
87+
CLK_OUT:
88+
dir: output
89+
desc: Fabric clock output
90+
Q[WIDTH-1:0]:
91+
dir: output
92+
desc: Data output
93+
DATA_VALID:
94+
dir: output
95+
desc: DATA_VALID output
96+
DPA_LOCK:
97+
dir: output
98+
desc: DPA_LOCK output
99+
DPA_ERROR:
100+
dir: output
101+
desc: DPA_ERROR output
102+
*/
103+
{ "CLK_OUT", "Q", "DATA_VALID", "DPA_LOCK", "DPA_ERROR" },
104+
88105

89106
{ "Y" }, // LUT1 = 16,
90107
{ "Y" }, // LUT2 = 17,
@@ -103,18 +120,60 @@ namespace {
103120

104121
{ "O", "DLY_TAP_VALUE" }, // O_DELAY = 27,
105122

106-
// O_SERDES = 28,
107-
{ "CLK_OUT", "Q", "CHANNEL_BOND_SYNC_OUT", "DLY_TAP_VALUE" },
123+
/* O_SERDES
124+
OE_OUT:
125+
dir: output
126+
desc: Output tri-state enable output (to O_BUFT or inferred tri-state signal)
127+
Q:
128+
dir: output
129+
desc: Data output (Connect to output port, buffer or O_DELAY)
130+
CHANNEL_BOND_SYNC_OUT:
131+
dir: output
132+
*/
133+
{ "OE_OUT", "Q", "CHANNEL_BOND_SYNC_OUT", "DLY_TAP_VALUE" },
134+
135+
136+
/* O_SERDES_CLK
137+
CLK_EN:
138+
dir: input
139+
desc: Gates output OUTPUT_CLK
140+
OUTPUT_CLK:
141+
dir: output
142+
desc: Clock output (Connect to output port, buffer or O_DELAY)
143+
type: reg
144+
default: 1'b0
145+
PLL_LOCK:
146+
dir: input
147+
desc: PLL lock input
148+
PLL_CLK:
149+
dir: input
150+
desc: PLL clock input
151+
*/
152+
{ "OUTPUT_CLK" },
153+
154+
155+
/* PLL
156+
CLK_OUT:
157+
dir: output
158+
CLK_OUT_DIV2:
159+
dir: output
160+
CLK_OUT_DIV3:
161+
dir: output
162+
CLK_OUT_DIV4:
163+
dir: output
164+
SERDES_FAST_CLK:
165+
dir: output
166+
LOCK:
167+
dir: output
168+
*/
169+
{ "CLK_OUT", "CLK_OUT_DIV2",
170+
"CLK_OUT_DIV3", "CLK_OUT_DIV4",
171+
"SERDES_FAST_CLK", "LOCK" },
108172

109-
// O_SERDES_CLK = 29,
110-
{ "CLK_OUT", "Q", "CHANNEL_BOND_SYNC_OUT", "DLY_TAP_VALUE" },
111-
112-
// PLL = 30,
113-
{ "CLK_OUT0", "CLK_OUT1", "CLK_OUT2", "CLK_OUT3",
114-
"GEARBOX_FAST_CLK", "LOCK" },
115173

116174
// TDP_RAM18KX2 = 31,
117-
{ "RDATA_A1", "RDATA_B1", "RDATA_A2", "RDATA_B2" },
175+
{ "RDATA_A1", "RDATA_B1", "RDATA_A2", "RDATA_B2",
176+
"RPARITY_A1", "RPARITY_B1", "RPARITY_A2", "RPARITY_B2" },
118177

119178
// TDP_RAM36K = 32,
120179
{ "RDATA_A", "RPARITY_A", "RDATA_B", "RPARITY_B" },
@@ -186,7 +245,7 @@ bool is_I_SERDES_output_term(const std::string& term) noexcept {
186245
if (term.empty()) return false;
187246

188247
static std::regex re_iserdes_out{
189-
R"(DLY_TAP_VALUE=|CLK_OUT=|CDR_CORE_CLK=|Q=|DATA_VALID=|DPA_LOCK=|DPA_ERROR=|Q\[\d+\]=)" };
248+
R"(CLK_OUT=|Q=|DATA_VALID=|DPA_LOCK=|DPA_ERROR=|Q\[\d+\]=)" };
190249

191250
std::cmatch m;
192251
bool b = false;
@@ -209,10 +268,10 @@ bool is_O_SERDES_output_term(const std::string& term) noexcept {
209268
if (term.empty()) return false;
210269

211270
static std::regex re_oserdes_out{
212-
R"(CLK_OUT=|Q=|CHANNEL_BOND_SYNC_OUT=|DLY_TAP_VALUE=|Q\[\d+\]=)" };
213-
214-
std::cmatch m;
271+
R"(OE_OUT=|Q=|CHANNEL_BOND_SYNC_OUT=|Q\[\d+\]=)" };
272+
215273
bool b = false;
274+
std::cmatch m;
216275

217276
try {
218277
b = std::regex_search(term.c_str(), m, re_oserdes_out);
@@ -231,9 +290,6 @@ bool is_TDP_RAM36K_output_term(const std::string& term) noexcept {
231290
assert(!term.empty());
232291
if (term.empty()) return false;
233292

234-
// // TDP_RAM36K = 32,
235-
// { "RDATA_A", "RPARITY_A", "RDATA_B", "RPARITY_B" },
236-
237293
static std::regex re_RAM36K_out{
238294
R"(RDATA_A=|RPARITY_A=|RDATA_B=|RPARITY_B=|RDATA_A\[\d+\]=|RPARITY_A\[\d+\]=|RDATA_B\[\d+\]=|RPARITY_B\[\d+\]=)"
239295
};
@@ -258,12 +314,10 @@ bool is_TDP_RAM18KX_output_term(const std::string& term) noexcept {
258314
assert(!term.empty());
259315
if (term.empty()) return false;
260316

261-
// // TDP_RAM18KX2 = 31,
262-
// { "RDATA_A1", "RDATA_B1", "RDATA_A2", "RDATA_B2" },
317+
static CStr p =
318+
R"(RDATA_A1=|RDATA_A1\[\d+\]=|RDATA_A2=|RDATA_A2\[\d+\]=|RDATA_B1=|RDATA_B1\[\d+\]=|RDATA_B2=|RDATA_B2\[\d+\]=|RPARITY_A1\[\d+\]=|RPARITY_A2\[\d+\]=|RPARITY_B1\[\d+\]=|RPARITY_B2\[\d+\]=)";
263319

264-
static std::regex re_RAM18KX_out{
265-
R"(RDATA_A1=|RDATA_A1\[\d+\]=|RDATA_A2=|RDATA_A2\[\d+\]=|RDATA_B1=|RDATA_B1\[\d+\]=|RDATA_B2=|RDATA_B2\[\d+\]=)"
266-
};
320+
static std::regex re_RAM18KX_out{ p };
267321

268322
std::cmatch m;
269323
bool b = false;
@@ -281,6 +335,35 @@ bool is_TDP_RAM18KX_output_term(const std::string& term) noexcept {
281335
return b;
282336
}
283337

338+
bool is_PLL_output_term(const std::string& term) noexcept {
339+
assert(!term.empty());
340+
if (term.empty()) return false;
341+
342+
// { "CLK_OUT", "CLK_OUT_DIV2",
343+
// "CLK_OUT_DIV3", "CLK_OUT_DIV4",
344+
// "SERDES_FAST_CLK", "LOCK" }
345+
346+
static CStr p =
347+
R"(CLK_OUT=|CLK_OUT_DIV2=|CLK_OUT_DIV3=|CLK_OUT_DIV4=|SERDES_FAST_CLK=|LOCK=)";
348+
349+
static std::regex re_PLL_out{ p };
350+
351+
std::cmatch m;
352+
bool b = false;
353+
354+
try {
355+
b = std::regex_search(term.c_str(), m, re_PLL_out);
356+
} catch (...) {
357+
assert(0);
358+
b = false;
359+
}
360+
361+
//if (b)
362+
// lprintf("__PLL_output REGEX matched: %s\n", term.c_str());
363+
364+
return b;
365+
}
366+
284367
// string -> enum, returns A_ZERO on error
285368
Prim_t primt_id(CStr name) noexcept {
286369
if (!name or !name[0])

‎stars/src/file_readers/pln_primitives.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,9 +69,12 @@ inline bool prim_pin_is_output(Prim_t primId, const std::string& pinName) noexce
6969

7070
bool is_I_SERDES_output_term(const std::string& term) noexcept;
7171
bool is_O_SERDES_output_term(const std::string& term) noexcept;
72+
7273
bool is_TDP_RAM36K_output_term(const std::string& term) noexcept;
7374
bool is_TDP_RAM18KX_output_term(const std::string& term) noexcept;
7475

76+
bool is_PLL_output_term(const std::string& term) noexcept;
77+
7578
}
7679

7780
#endif

‎stars/src/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
static const char* _pln_VERSION_STR = "pln0231";
1+
static const char* _pln_VERSION_STR = "pln0233";
22

33
#include "RS/rsEnv.h"
44
#include "util/pln_log.h"

0 commit comments

Comments
 (0)