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lines changed- VERSION.md+1-1
- docs/source/manual/file_formats/clock_network.rst+10-5
- openfpga/src/utils/openfpga_physical_tile_utils.cpp+8-10
- openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml+214
- openfpga_flow/regression_test_scripts/basic_reg_test.sh+1
- openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/clk_arch_1clk_2layer.xml+25
- openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/task.conf+42
- openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/tile_config.xml+1
- openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml+506
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